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shumaguandongtaixianshi
- 实现开发板上8 个数码管动态显示0~7。通过这个实验，掌握采用Verilog HDL 语言编程实现7 段数码管显示译码器以及数码管动态扫描显示的方法。-Development board 8 digital tube dynamic display from 0 to 7. Through this experiment, master the 7-segment LED display decoder and digital tube dynamic scan display method
base-paper
- this the base paper for tcm decoder in verilog-this is the base paper for tcm decoder in verilog
my38decoder
- 这个是用verilog语言写的一个38译码器的程序，在DE2最小系统板里验证过 -This is to use verilog language is written a and decoder program, in DE2 minimum system board validated
newViterbi217
- 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct
3_8yimaqi
- FPGA verilog 3-8 译码器-FPGA verilog 3-8 decoder
decoder_3to8
- decoder 3 to 8 verilog program
decoder_5to32
- verilog 5 to 32 decoder
RS_dec
- rs（204,188）译码器，verilog实现，乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
ymq_38
- 此代码运用verilog语言实现38译码器，在led来显示结果。-This code use verilog language realization and decoder, in led to display the results.
bluespec-reedsolomon_latest.tar
- Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
decoder_3_8
- FPGA的3-8译码器，使用Verilog编写-3-8 FPGA decoder in Verilog
q_74ls138
- 在quartus II 9.1上用verilog原理图形式实现的74ls138功能的38译码器-38 of 74ls138 features achieve verilog schematic form in quartus II 9.1 decoder
eda-Lab-report
- 三线八线译码器、数据选择器、数据比较器、二进制编码器、译码器的verilog语言输入方法-Three line eight line decoder, data selector, comparator, the binary encoder and decoder of verilog language input method
635026760674375000
- verilog语言编写的一些数字器件.包括译码器，编码器，D触发器等-Verilog language of some digital devices. Including decoder and encoder, D flip-flop, etc
C3_8
- fpga verilog HDl 38译码器 组合逻辑电路-fpga Verilog HDL 38 decoder combinational logic circuit
Control_Display
- Controlador de display siete segmentos en verilog El archivo contiene selector decodificador multiplexor y archivo para simulacion Sevent segment dispay controler in verilog for basys nexys2 nexys3 fpga boards This file have a decoder, selector
adsawfd
- 用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平 用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disa
project2_1
- 3:8译码器，HDl verilog语言编写，能在DE2上运行-3:8 decoder, HDl verilog language, able to run on the DE2
project2_2
- 7段译码管，用于显示数字，HDl verilog语言编写，能在DE2上运行-7 segment decoder tube used to display numbers, HDl verilog language, can be run on the DE2
Enc_With_Punc---2011-11-28-v3.0
- Viterbi 译码打孔和去打孔代码, ,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,