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E_8051_FTEST_K4X4_new
- 是带５１单片机核的等精度频率计的ＦＰＧＡ设计的部分。用ＶＨＤＬ编的，也有ＶＥＲＩＬＯＧ的。-51 is a single chip with precision, such as the nucleus of the frequency of some of FPGA design. VHDL for use as well as the VERILOG.
AD9851_VERILOG
- 一个DDS芯片AD9851的VERILOG程序，加74HC574锁存器！-A DDS chip AD9851' s VERILOG program, plus 74HC574 latch!
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
chuzhuchejifeiqi
- 利用FPGA芯片控制出租车计费系统，采用Verilog HDL编写，程序简介-Control the use of FPGA chip Taxi billing system, using Verilog HDL preparation, procedures for
NIOS_NET_demo
- 在nios系统开发中的网卡芯片驱动的代码,包括verilog代码,与相应的驱动代码-In the nios system development in the card chip-driven code, including the verilog code, and the corresponding driver code
ADC124
- 采用verilog编写的高速串型AD采集芯片adc124驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
shuzishizhong
- 用verilog语言写的数字时钟程序 芯片是EP2C8Q208C8-Verilog language used to write the digital clock program chip EP2C8Q208C8
THS1206
- 运用verilog对ad1206芯片进行控制，对信号进行采样的信号，已通过测试-Using verilog on ad1206 chip control, the signal is sampled signals, has been tested
VerilogEP2C8Q208PLL_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序 PLL_12MHz-Verilog HDL language EP2C8Q208 chip PLL frequency of the simple program PLL_12MHz
USB_LOOP
- 该Verilog程序基于USB芯片68013,FPGA50T,实现了两台电脑之间使用两个68013和一个FPGA50T来通信-Verilog program is based on the USB chip 68013, FPGA50T, realized between two computers using two 68013 and one FPGA50T to communicate
lcd12864_EP3C10
- 在quartusII下开发的lcd12864的verilog程序，方便大家的学习。本程序基于EP3C10T144芯片-Developed under the quartusII lcd12864 the verilog program to facilitate everyone' s learning. The program is based on EP3C10T144 chip
foundatonise
- WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256 -6) -WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256-6)
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
ads7809
- ADS7809是Burr-Brown公司推出的高精度AD采集芯片。它采用5V单电源供电,内含16位 逐次逼近寄存器,采样精度高,功耗小。 用Verilog实现其配置-ADS7809 is a Burr-Brown Introduces High Precision AD capture chip. It uses a single 5V supply, with 16-bit successive approximation register, sampling and high pre
Leg8
- 待商业化的8位高速cpu芯片设计，verilog语言编译通过，ISE平台完成-To be commercial cpu 8-bit high-speed chip design, verilog language compiler, ISE platform to complete
TLC549
- 以Verilog描绘的有关于芯片TLC549的驱动程序-Described in Verilog on the driver chip TLC549
20104169105873879
- 主要功能：pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言，使用器件是Cyclone2，应用于其他FPGA时，直接调整管脚即可。-Main features: pci9054 local bus control chip sample program can be used for pci driv
DAC0832_control
- 用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制-Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control
cpld_10fenpin
- 针对cpld芯片采用verilog编程实现的10分频程序。附带其功能仿真文件。-For cpld chip verilog programming of 10 frequency program. With its functional simulation file.
honglvdeng
- Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。他的设计描述可被不同的工具所支持,可用不同器件来实现。利用Verilog HDL语言自顶向下的设计方法设计交通灯控制系统，使其实现道路交通的正常运转，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Xilinx ISE6.02和ModelSim5.6完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的交通灯控制系统中。-Verilog HDL as a standard hardware