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doorlock.rar
- 门锁 状态机 verilog 适用于digilent NEXYS2开发板,doorlock state machine verilog applied to digilent NEXYS2 board
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
lcd
- 这是一个用verilog写的LED的控制代码，其中主要是利用状态机的形式实现的-This is a verilog the write LED control code, which is realized in the form of state machine
ps_transfer
- verilog HDL语言编写的8位并串转换，使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ，can comprehense
SoftDrink
- 用Verilog编写的自动售货机控制程序，在cyclon DE2开发板上测试通过，建议用Quartus 10.1编译。-Vending machine control program written using Verilog test by in cyclon DE2 development board, we recommend using Quartus 10.1 compiler.
uart_state
- 基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC
chao
- 利用有限状态机实现一般时序逻辑分析的方法； 进掌握用Verilog编写的有限状态机的标准模板-Finite state machine to achieve general sequential logic analysis method into the grasp of finite state machines using Verilog standard template
USB
- 此例程是基于FPGA的USB控制器实例，主要功能为通过FPGA芯片控制USB芯片，实现开发板和PC机之间的USB接口数据通信，来模拟一个硬件加密设备的功能。用Verilog语言实现。-This routine is an instance of the USB controller based on FPGA, the main function is to control USB chip by the FPGA chip, implement the USB interface for da
clock
- 一个简单的数字时钟Verilog仿真程序，60秒1分钟，60分一小时，24小时一天，265天一年。代码逻辑简化不含状态机，易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to
Golf_Test
- 用verilog语言实现的高尔夫模拟机下位机检测，参数包括速度、仰角和偏角。-Verilog language golf simulator under-bit machine detection parameters include speed, elevation and declination.
MIPSCPU
- 用verilog描述一个mips体系结构的cpu，分别用c语言mips汇编语言写了一段程序，翻译成机器码可以再cpu上运行。仿真结果三者完全一致。-Mips architecture cpu with verilog descr iption c language mips assembly language to write a program, translated into machine code can then cpu running on. Simulation results e
state_machine
- verilog编程状态机实战训练：1.本实例通过实现一个状态机来控制8个LED循环闪亮； 2. 工程在project文件夹里面； 3. 源文件和管脚分配在rtl文件夹里面； 4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.
ram2114
- 本程序是利用ise平台设计出的ram2114的Verilog源代码，通过上机运行检测。-This procedure is to use the platform to design a ram2114 ise of Verilog source code, the test is run through the machine.
Reg_16
- 用Verilog语言实现简单的16位状态机-Use Verilog language to design a 16 state machine
Seven-voting-machines
- 用verilog编写的七人表决器代码·可以实现七人表决超过四人就通过的功能-Written in verilog seven voting machine code can be achieved seven people to vote on the adoption of more than four functions
shixuzhuangtaiji
- 通过verilog hdl语言实现对时序状态机的编写-By verilog hdl language for writing timing state machine
sale22222222
- fpga verilog语言写的自动售货机-fpga verilog language written vending machine
shj
- 基于fpga的自动售货机，verilog编写，源码内有详细说明-Fpga-based vending machine, verilog prepared with a detailed descr iption of source