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vending-machine
- vending machine in verilog
state-machine
- Verilog HDL编写的简单状态机程序。-The Verilog HDL written a simple state machine program.
I2C_IP-Verilog
- i2c代码，包含主机，从机以及相关测试代码-the i2c code contains the host from the machine as well as the relevant test code
Vending-machine
- 使用verilog语言编写的自动售货机按钮，可以实现简单的售货功能-Vending machines using Verilog language button, you can achieve a simple function of goods sold
Verilog-FSM(TSC)
- Finate State machine
UART-finite-state-machine
- 基于Verilog语言的，用有限状态机实现Uart，很实用-UART design based on finite state machine
WASHING-MACHINE-2012Verilog
- Verilog语言编写的自动洗衣机控制程序，数字系统课程设计-Verilog language automatic washing machine control program, digital systems curriculum design
finite state machine
- finite state machine in verilog use quartus to program it into FPGA
vending-machine
- 用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。-Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.
vending-machine
- 自动售货机，5角1元输入，三种饮料输出，余额不足或售完会闪烁相关信息。-THis is a simulator of Vending Machine on Basys2 in verilog. 5jiao and 1yuan as input, 3 chioces for drinks. If all are sold out or more money is need, corresponding signals will flash on the LED screen.
The-four-locks-Verilog-based-design
- 基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation
Verilog
- Verilog课程设计自动售货机 1）设计一个自动售货机，此机能出售1.5元、2元两种商品。出售哪种商品可有顾客按动相应的一个按键即可，并同时用数码管显示出此商品的价格。可同时购买两种、多件商品。 2）顾客投入硬币的钱数有5角、1元两种。此操作通过按动相应的两个按键来模拟，并同时用数码管将投币额显示出来。 3）顾客投币后，按一次确认键，如果投币额不足时则报警灯亮。如果投币额足够时自动送出货物（送出的货物用相应不同的指示灯显示来模拟），同时多余的钱应找回，找回的钱数用数码管
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
Verilog-HDL-washer
- 智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
Verilog-example3
- verilog实例分析第三部分，通过实例分析讲解有限状态机的设计过程。-The third case study verilog part, by an example to explain the finite state machine design process.
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
State mchine
- State machine in Verilog
state-machine
- A verilog implementation of a state machine example.
state-machine
- 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word