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利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
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推荐下载,verilog状态机实例.体现了流水线思想的应用
-recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
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强烈推荐下载,verilog状态机实例.可以在modelsim下运行.
-strongly recommend downloading Verilog state machine example. In modelsim running.
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交通灯状态机的实现,用verilog HDL编程,Xilinx ISE 6仿真,在实际电路中得到验证.-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
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Verilog三段式状态机描述,本章内容详细的介绍了Verilog三段式状态机描述,进一步加深对Verilog的认识-Verilog descr iption of three-stage state machine, this chapter introduces Verilog detailed descr iption of three-stage state machine, and further deepen the understanding of Verilog
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verilog语言, 状态机实现数码管显示
-This uses verilog language to make state machine realization of digital control
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Verilog and VHDL状态机设计,内含源代码,希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
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如何写好状态机,用verilog。状态机很方便。-How to write a state machine, with verilog. State machine is very convenient.
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Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
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Verilog三段式状态机.pdf
Verilog时序电路及状态机设计.ppt
Verilog有限状态机设计.ppt
状态机.ppt
用状态机原理进行软件设计.pdf
有限状态机.pdf
有限状态机.ppt
状态机原理及用法.pdf
对状态机初学者有帮助。
-Verilog three-state machine the pdf Verilog Sequential Circuits and the state machine design. Ppt Veri
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简易状态机 verilog实现的简单状态机,全工程不错的 典型历程 值得学习入门很好的实验例程-Simple state machine verilog achieve a simple state machine, the typical course of the whole works good deserves learning entry good experimental routines
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Verilog HDL编写的简单状态机程序。-The Verilog HDL written a simple state machine program.
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基于Verilog语言的,用有限状态机实现Uart,很实用-UART design based on finite state machine
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finite state machine in verilog use quartus to program it into FPGA
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状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
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A verilog implementation of a state machine example.
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verilog状态机实验,说明一个状态机的生成过程(Verilog state machine experiment, which illustrates the generation process of a state machine)
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千兆网学习代码 ISE,状态机实现数据打包,基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
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学习FPGA的入门书籍,主要内容包括:逻辑电路、组合逻辑、算术运算电路、存储元件、同步时序电路(有限状态机)、异步时序电路、测试等。《数字逻辑基础与Verilog设计》(原书第2版)内容全面,概念清楚,结合了逻辑设计最新技术的发展。(Learn the introductory books of FPGA. The main contents include logic circuit, combinational logic, arithmetic operation circuit, sto
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采用Verilog语言设计一个序列信号发生器和一个序列信号检测器,二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”,通过数码管显示出来;序列信号发生器的输出接入序列信号检测器,检测器检测当前的输入信号,若出现目标序列信号则通过蜂鸣器输出一个声响,表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b
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