采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, both of which are implemented in a state machine mode. The sequence signal generator outputs an 8-bit wide sequence signal "10110110", which is displayed through the digital tube; the output of the sequence signal generator is connected to the sequence signal detector, the detector detects the current input signal, and if the target sequence signal appears, it passes through the bee. The horn emits a sound indicating that a valid target signal has been detected.)