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搜索资源 - Verilog state machine
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这是一个verilog HDL语言代码,主要利用状态机控制数码管,从0到9循环显示。-This is a verilog HDL language code, the main use state machine control digital tube, from 0 to 9 cyclic display.
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雷鸟车尾灯设计,采用VERILOG语言开发,大家可以逐渐熟悉状态机实验。-Thunderbird car taillight design, using VERILOG language, everyone can become familiar with the state machine experiment.
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verilog写ps2接口驱动程序,对状态机的描述。把键盘串行的13为数据转换为并行的8为数据,并储存在寄存器-The needle verilog write ps2 interface drivers, to the descr iption of the state machine. The keyboard for data transfer of serial and parallel for the 8 for data, and stored in a register to xi
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原创,帧同步器的Verilog代码,在FPGA上验证实现过,无误。作为通信系统帧传输的仿真,有限状态机同步态和失步态的切换仿真。-Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine sync
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FPGA实现 LCD1602 显示 PS/2 键盘的键值,熟悉并掌握液晶 1602 显示屏的使用方法及PS/2键盘的接口标准,学习利用Verilog-HDL语言编写有限状态机实现较为复杂的设计与应用。-LCD1602 FPGA realizing that the PS/2 keyboard keys, familiar with and master the use of liquid crystal display 1602 method and PS/2 keyboard interfac
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1、用FPGA/CPLD实现HS162字符液晶显示。
2、分析相应的功能要求,分析CPLD与字符液晶HS162的接口典型电路。
3、利用状态机的设计方法,通过指令编程实现对HS162-4液晶模块的读/写操作,以及屏幕和光标的操作。
4、编写模块的Verilog HDL语言的设计程序。
5、在Quartus II软件或其他EDA软件上完成设计和仿真。
-This design of a CPLD-based controls HS162 to achieve character
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moore异步状态机verilog实现,通过异步时钟和两个输入来对输出的状态进行控制,比同步状态机有更广泛的应用。-the moore asynchronous state machine verilog implementation, asynchronous clock and two input to the output state control, have a much wider application than the synchronous state machine.
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一些复杂逻辑电路的设计,状态机的verilog的程序语言-The design of complex logic circuits, the state machine of the verilog programming language
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关于状态机的规范编码风格,有具体的verilog,vhdl实例-On the norms of the state machine coding style, specific Verilog, VHDL instance
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本代码在FPGA上使用Verilog编程语言实现LCD1602驱动(使用状态机)-This code using Verilog programming language achieved LCD1602 driver (using the state machine) on the FPGA
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本代码使用Verilog语言编写的带状态机的数码管驱动并在FPGA上得到验证!-This code uses the Verilog language with digital tube-driven state machine to be verified on the FPGA!
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本代码使用Verilog语言实现了矩阵键盘的驱动(含状态机)-This code uses the Verilog language matrix keyboard driver (including the state machine)
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<p>交通灯状态机的实现,用verilog HDL编程与开发,Xillinx ISE 6仿真,在实际电路中的到验证. 已通过测试。</p>
-<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulation, to verify the actual circui
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verilog finite state machine program
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状态机,检测状态110,小演示程序,可直接运行,verilog hdl-State machine, the detection state 110, a small demo program can be run directly, verilog hdl
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使用Verilog编写的实现FPGA键盘功能,使用了状态机-The use of FPGA in Verilog keyboard function, using the state machine
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verilog程序源码,实现两个16bit数乘法,使用booth算法,一种基于状态机实现,分层层次为datapath与controller两个子模块,testBench测试通过
-verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the hierarchical level for the da
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用VERILOG HDL编写的通过状态机控制步进电机的例程,很经典-VERILOG HDL prepared by the state machine to control the stepper motor routines, classic
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简单的跑马灯verilog程序,笔者是初学者,利用简单状态机编写的-Simple Marquee verilog program, the author is a beginner, use a simple state machine to write
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朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。
-Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
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