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用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
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交通灯控制器的Verilog代码，采用了三段式的状态机描述，适合学习和练习，包括了验证代码-A Verilog code of Traffic light controller, using a three-stage state machine descr iption suitable for learning and practice, including the verification code
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电梯程序 用verilog实现 经过quartus验证-Elevator after quartus verification procedures with verilog
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十六分频verilog代码，经过quartus验证-16 divided verilog code verification after quartus
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8255IO的verilog描述语言，仅包含模式零，运行正确，经过调试验证。可放心使用-8255IO the verilog descr iption language of, contains only mode zero, properly run, verification after commissioning. Can be assured
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This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
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This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
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This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
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it is the verification code written in system verilog for the verification of 4:1 mux and with functional coverage
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xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
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解析verilog代码的perl脚本，解析结果可用于一系列验证自动化-Verilog code parsing perl scr ipt that the analytical results can be used to automate a series of verification
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目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
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采用Verilog编写的4x4矩阵键盘的程序。该程序经过验证可行。-Implementation of 4x4 matrix keyboard Verilog language. After verification, the feasible.
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verilog实现输出锯齿波形，已经通过DA芯片验证通过-verilog to achieve the output sawtooth waveform, has passed through the DA chip verification
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本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中
Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面，
是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
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system verilog with universal verification methodology
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关于CRC的发射，以及接受的验证，用Verilog实现，包含testbench验证-About CRC launch, as well as acceptable verification, using Verilog implementation, including verification testbench
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设计与验证Verilog HDL 可以-Verilog HDL design and verification
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本压缩包含了3个关于VGA显示的程序，都是用Verilog编写的，经过程序编译验证，确定可行。-This archive contains three procedures on the VGA display, are using Verilog, after verification program is compiled to identify viable.
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AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
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