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文件名称:cpld_ads7844_50M(9-24)

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    642kb
  • 已下载：
    1次
  • 提 供 者：
    王***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpld_ads7844_50M(9-24)/
cpld_ads7844_50M(9-24)/ads7844_caiji_module.v
cpld_ads7844_50M(9-24)/ads7844_caiji_module.v.bak
cpld_ads7844_50M(9-24)/ads7844_uart.asm.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.cdf
cpld_ads7844_50M(9-24)/ads7844_uart.done
cpld_ads7844_50M(9-24)/ads7844_uart.dpf
cpld_ads7844_50M(9-24)/ads7844_uart.eda.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.fit.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.fit.smsg
cpld_ads7844_50M(9-24)/ads7844_uart.fit.summary
cpld_ads7844_50M(9-24)/ads7844_uart.flow.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.map.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.map.smsg
cpld_ads7844_50M(9-24)/ads7844_uart.map.summary
cpld_ads7844_50M(9-24)/ads7844_uart.pin
cpld_ads7844_50M(9-24)/ads7844_uart.pof
cpld_ads7844_50M(9-24)/ads7844_uart.qpf
cpld_ads7844_50M(9-24)/ads7844_uart.qsf
cpld_ads7844_50M(9-24)/ads7844_uart.qws
cpld_ads7844_50M(9-24)/ads7844_uart.tan.rpt
cpld_ads7844_50M(9-24)/ads7844_uart.tan.summary
cpld_ads7844_50M(9-24)/ads7844_uart.v
cpld_ads7844_50M(9-24)/ads7844_uart.v.bak
cpld_ads7844_50M(9-24)/db/
cpld_ads7844_50M(9-24)/db/ads7844_uart.(0).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(0).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(1).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(1).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(2).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(2).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(3).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(3).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(4).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(4).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(5).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(5).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(6).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(6).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(7).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(7).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(8).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(8).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(9).cnf.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.(9).cnf.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.asm.qmsg
cpld_ads7844_50M(9-24)/db/ads7844_uart.asm_labs.ddb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cbx.xml
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.kpt
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.logdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.rdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp.tdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.cmp0.ddb
cpld_ads7844_50M(9-24)/db/ads7844_uart.db_info
cpld_ads7844_50M(9-24)/db/ads7844_uart.eco.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.eda.qmsg
cpld_ads7844_50M(9-24)/db/ads7844_uart.fit.qmsg
cpld_ads7844_50M(9-24)/db/ads7844_uart.hier_info
cpld_ads7844_50M(9-24)/db/ads7844_uart.hif
cpld_ads7844_50M(9-24)/db/ads7844_uart.lpc.html
cpld_ads7844_50M(9-24)/db/ads7844_uart.lpc.rdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.lpc.txt
cpld_ads7844_50M(9-24)/db/ads7844_uart.map.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.map.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.map.logdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.map.qmsg
cpld_ads7844_50M(9-24)/db/ads7844_uart.pre_map.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.pre_map.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.rtlv.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.rtlv_sg.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.rtlv_sg_swap.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.sgdiff.cdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.sgdiff.hdb
cpld_ads7844_50M(9-24)/db/ads7844_uart.sld_design_entry.sci
cpld_ads7844_50M(9-24)/db/ads7844_uart.sld_design_entry_dsc.sci
cpld_ads7844_50M(9-24)/db/ads7844_uart.smp_dump.txt
cpld_ads7844_50M(9-24)/db/ads7844_uart.syn_hier_info
cpld_ads7844_50M(9-24)/db/ads7844_uart.tan.qmsg
cpld_ads7844_50M(9-24)/db/ads7844_uart.tis_db_list.ddb
cpld_ads7844_50M(9-24)/db/ads7844_uart.tmw_info
cpld_ads7844_50M(9-24)/db/ads7844_uart_global_asgn_op.abo
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.asm.qmsg
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.eda.qmsg
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.fit.qmsg
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.map.qmsg
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.qmsg
cpld_ads7844_50M(9-24)/db/prev_cmp_ads7844_uart.tan.qmsg
cpld_ads7844_50M(9-24)/detect_module.v
cpld_ads7844_50M(9-24)/incremental_db/
cpld_ads7844_50M(9-24)/incremental_db/README
cpld_ads7844_50M(9-24)/incremental_db/compiled_partitions/
cpld_ads7844_50M(9-24)/incremental_db/compiled_partitions/ads7844_uart.root_partition.map.kpt
cpld_ads7844_50M(9-24)/rx_bps_module.v
cpld_ads7844_50M(9-24)/rx_bps_module.v.bak
cpld_ads7844_50M(9-24)/rx_control_module.v
cpld_ads7844_50M(9-24)/rx_module.v
cpld_ads7844_50M(9-24)/simulation/
cpld_ads7844_50M(9-24)/simulation/modelsim/
cpld_ads7844_50M(9-24)/simulation/modelsim/ads7844_uart.sft
cpld_ads7844_50M(9-24)/simulation/modelsim/ads7844_uart.vo
cpld_ads7844_50M(9-24)/simulation/modelsim/ads7844_uart_modelsim.xrf
cpld_ads7844_50M(9-24)/simulation/modelsim/ads7844_uart_v.sdo
cpld_ads7844_50M(9-24)/tx_bps_module.v
cpld_ads7844_50M(9-24)

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