搜索资源列表
Viterbidecoder
- 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Viterbi_v
- Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
viterbi_decoder_sources_code_verilog
- viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Viterbi_RAKE
- 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着
bianmaqi
- 一个完整的viterbi(2,1,7)编码程序，使用的是Verilog语言
viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
VB_decode
- Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
Control
- 维特比译码器控制器部分Verilog代码-The controller part of the Viterbi decoder in Verilog code
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Viterbi_Verilog
- viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
viterbi
- 维特比译码，卷积编码，verilog编写，2,1,2编码-Victor than decoding, convolution code, verilog write, 2,1,2 coding
viterbi_decoder_axi4s
- Viterbi译码器的verilog代码和测试-Verilog code and testing of the Viterbi decoder
convotion_decode
- 用verilog写的卷积码的编码程序以及viterbi译码程序-Use verilog write convolution code coding procedures and viterbi decoding program
Viterbi
- viterbi 译码相关算法讲解和Verilog代码，代码已经通过仿真验证没问题。-viterbi decoding algorithm explanation and Verilog code, the code has been verified by simulation problems.
viterbi
- 维特比译码相关verilog代码，基于802.11g协议的。。
VITERBI
- viterbi编码算法verilog实现-viterbi encoder, developed by verilog language
VITERBI
- In this case is a viterbi algorithm code for decoding the convolutional code, using verilog HDL language. This code provide the method of deconvolution of the convolutional code
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
verilog
- VITERBI DECODER MODULE This module implements the FSM and instantiation of all the modules used for Viterbi decoding.