搜索资源列表
VLSI_CA1.tar
- this the implementaion of an 8-bit mirror adder in Verilog-this is the implementaion of an 8-bit mirror adder in Verilog
par_addsub
- adder subtreactor verilog code
3bit_adder
- Verilog source code for a 3bit full adder build with modules using predefined nand gates.
booth4
- 4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写-4-bit adder booth algorithm, the learning of computer organization help, verilog language
four_bit_addersubtractor
- Verilog code for 4 bit Adder/Subtructor
adder4
- 此源代码是基于Verilog语言的4 位全加器，4 位计数器、 4 位全加器的仿真程序、4 位计数器的仿真程序是用EDA语言描述4 位全加器，有广泛的应用。-The Verilog language source code is based on the 4-bit full adder, 4 bit counter, 4-bit full adder simulation program, 4-bit counter of the simulation program is to use la
ADD6
- 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to ac
Desktop
- it s a file contain Verilog code of a full adder. I hope this file is usefull for someone ! Regards !
add83coder
- 实现加法器和83译码器的功能！写的很好的verilog程序！-Adder and 83 to achieve the function of the decoder! Verilog to write a good program!
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
full_adder
- 用verilog在半加器的基础上实现了全加器，方法简单巧妙，对于FPGA入门学习很有帮助-In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter
Simple_Verilog_Code_For_Beginner
- verilog code for beginner (adder, comparator, mux, or, and subtractor)
fpuvhdl_latest
- the code describle a floating point adder with verilog
F_ADD
- a adder with verilog-a adder with verilog
addersubtractor
- adder subtractor...this source is example to build adder and subtractor code in verilog (.v)
picenter
- signed adder simple verilog module ... working
cla20_n
- Verilog 20 bit的累加器 采用流水香设计，用5级4bit的超前进位加法器-Verilog 20 bit accumulator using water in Hong design, with five 4bit the look-ahead adder
4b_ripple_carry_full_adder
- ripple carry for full adder of 4- bit in verilog
Adder_2bit
- 2位加法器，采用Verilog语言编写，在开发板上经过验证，希望对大家有所帮助-2-bit adder using the Verilog language, proven in the development board, we hope to help
adder_32bit
- 以ISE为平台，用Verilog编写的32位全加器模块，只需在Top模块中调用即可-The ISE as a platform, written with Verilog 32-bit full adder module, simply call the module to Top