搜索资源列表
adder4
- 利用硬件语言FPGA Verilog语言实现4位加法器的运算-Using FPGA hardware language Verilog language implementation and operation of four adder
adder5
- 5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。-5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
FA
- 使用VERILOG實現全加器的設計,並附上TB供測試-Use VERILOG achieve full adder design, together with a test for TB
add_10
- FPGA中基于Verilog语言的10位加法器设计，适合初学者学习FPGA-FPGA Verilog language-based 10-bit adder design, suitable for beginners to learn FPGA
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
half_sub
- 用Verilog语言实现的半加器功能，非常好的例程。-Verilog language implementation with half adder function, very good routine.
ISEadder
- 利用Verilog语言，基于ISE，设计加法器-ISE adder
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
Accumulator
- An 8-bit Accumulator with an adder module in Verilog HDL. You can change the bus width decoding the adder.
paralleladder
- This a verilog source code for parallel adder-This is a verilog source code for parallel adder
HW-02-13210140
- Verilog code adder for add 2 16bit in parallel-adder for 16bit used to add two bits in parallel. this code in verilog languanger
module002268.tar
- this verilog code of adder-this is verilog code of adder
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
quanjiaqi
- 使用verilog HDL实现全加器的功能-Use verilog HDL to achieve full adder function
4weijianfaqi_verilog
- 四位加法器的verilog实现，用VHDL语言，附tb.v。-Verilog achieve four adder, using VHDL language, with tb.v.
lab7_adders3
- 加法器的verilog实现，第二种方法：超前进位加法器 -Another implementation of adder in verilog
mixed-language--desvription-of-a-4x4-comparator.z
- mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
bcdflag
- verilog code bcd adder using flag register