搜索资源列表
Adder_12bit
- 带进位的12位宽超前进位加法器,可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.
book3e
- 数字信号处理的FPGA实现随书光盘,包含大量Verilog代码,包括加法器,乘法器以及FIR滤波器设计,快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
half_band
- 半带滤波器verilog源代码,主要用于采样率变换系统中,采用乘法积累加器,很好的例子,供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
adder_32bits
- 采用“进位选择加法”技术设计32位加法器 Verilog语言编写-32 bit adder
bcd_adder
- BCD ADDER USING VERILOG
RSFQ_Adder
- fpga implementation of rsfq adder using verilog code
parallel_prefix_flag
- design of parallel prefix adder in verilog
halfadder
- IT IS A VERILOG PROGRAM FOR HALF ADDER.
demoss
- FPGA的代码verilog语言编写,包括LED与按键验证,数据选择器,编码器,译码器半加器,全加器,适合初学者,已经在板子调试成功,板子是 睿智IV开发板。-FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been succe
accumulator
- 一个简单的加法器实现程序,已验证,使用的是Verilog HDL编写,适合初学者入门学习-A simple adder procedures, verified, using Verilog HDL prepared, for beginners to learn
accsub
- 简单的加法器减法器程序代码,Verilog HDL初学者学习可以使用-Simple adder subtractor code, Verilog HDL beginners can use
FPGA__source-code__Verilog
- FPGA部分基础功能源代码,适合初学者进行学习仿真,代码可读性强,通俗易懂,逻辑清晰。包括触发器,全加器,分频,并串转换,计数器,序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
Verilog_32bit_Adder
- 32位超前进位加法器的改进Verilog实现-Improved Verilog implementation of 32 bit ahead carry adder
L-CLA20_20-code.
- DHL CLA20_20 development with the Verilog bit ahead carry adder code.
add
- 硬件描叙语言实现一个加法器,开发环境使用的是libreo,用的是Verilog语言-Hardware descr iption language to realize an adder, development environment using the libreo, with Verilog language
full_add
- full adder in verilog
half_add
- half adder in verilog
p3structural
- To Design 1-bit Full Adder using Verilog HDL for all logic gates with switch and gate level modelling.
Adder_4bit
- Verilog Program for a 4bit Adder
full_adder
- 用verilog语言编写的全加器模块代码,在ISE软件环境下编译开发,希望对大家有所帮助!-With verilog language full adder module code in ISE software compiler development environment, we want to help!