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verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
adder
- 涉及半加器与全加器的电路连线图模块。非语言编写。-FPGA-verilog,full_adder and half_adder.
adder_verilog
- This file is a four bit adder verilog code. its function is to add. it has other verilog files as we-This file is a four bit adder verilog code. its function is to add. it has other verilog files as well
add
- 浮点加法器的用Verilog实现，32位的浮点加法器-Floating point adder Verilog
Verilog-fpga-cailiao
- 这是fpga板子自带的verilog程序，包含流水等 彩灯，加法器，减法器，等多个程序！-This is the verilog fpga board comes with the program, including water and other lights, adder, subtractor, and other programs!
Desktop
- adder verilog. is not c language. just an adder in verilog
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
Fast-adder-design-using-verilog
- 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
CarryLookaheadAdder64
- 一个64位超前进位加法器，verilog语言描述。-A 64 bits carry look ahead adder, verilog
acc
- 全加器，比较器等verilog hdl代码 以及测试代码-Full adder verilog hdl code of the comparator
Verilog-examples
- verilog 例程，白金手册，很多实用例程，加法器，循环编码器-verilog routines, platinum manual, many utility routines, adder, cycle coding and more
adder
- This the program for addition in verilog-This is the program for addition in verilog
adder
- 可加可减器，使用verilog编写，4位加减器。-Can be increased or decreased, verilog prepared 4 addition and subtraction.
adder
- adder in verilog only with combinational logic use
full_a4
- 4位全加器的verilog程序设计-Four full adder verilog programming ...
ser_adder
- 串入串出加法器 verilog 代码 串入串出加法器 verilog 代码-serial adder verilog code serial adder verilog code
Verilog
- 基于Verilog语言的循环式加法器的设计,是中国科技大学电子与科学系论文-Cycle adder design based on Verilog language, University of Science and Technology of China Electronic Science thesis
ripple_carry_adder
- 行波加法器，Verilog语言编写。行波加法器，Verilog语言编写-The line wave adder Verilog language. The line wave adder Verilog language
add
- 用verilog实现加法器程序，通过仿真验证-Adder verilog achieve program is verified by simulation
float
- 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language