搜索资源列表
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
ps2andverilog
- 仿真已通过验证，并下载到FPGA实验板测试，大家可以下载来学习-Simulation has been validated, and downloaded to the FPGA test board test, you can download to learn ~~~~~
PWM_DA
- 可以产生PWM波形文件 ，熟悉基于FPGA的开发流程 自己写的程序-PWM waveform files can be generated, FPGA-based development process familiar to write their own programs
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
1
- 使用force和release语句，这种方法不能准确反映双向端口的信号变化，但这种方法可以反映块内信号的变化。具体如示：-Use of force and release statements, this method does not accurately reflect the bi-directional port of the signal changes, but this method can reflect the changes in the signal block. Spec
uart
- verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
SPItoI2S
- 该文件是I2S 转 SPI的Verilog的源代码，可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
verilog
- 两本非常好的Verilog入门学习资料，Verilog程序设计135例，Verilog经典教程，通过学习此教程，可基本掌握Verilog。-Two very good entry-learning materials Verilog, Verilog programming 135 cases, Verilog classic tutorial, by learning this tutorial, you can master the basic Verilog.
traffic_lights
- Verilog 语言实现的红黄绿交通灯程序，编译成功，为全工程文件，可以直接打开运行-Verilog language of the red yellow and green traffic lights program, compile successfully, for the whole project file, you can directly open the run
IP
- this a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .-this is a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can dow
sourceInsight-lan
- souceinsight软件的语言解析文件，用于高亮关键字，开发浏览代码时，有所帮助。-DeviceIOControl, vc in io shows how to direct the operation of the underlying need friends can learn about.
VGA_TEST
- 用verilog HDL实现的VGA接口，调试成功，能直接使用-Implemented using verilog HDL VGA interface, debugging success, can be used directly
VGA
- VERILOG编写的VGA实验例程，包括整个工程，可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
CoreCFI
- VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
vga800-600
- Verilog语言实现的 VGA 显示器的 汉字和字符显示！！已经编译成功，可以直接使用-VGA monitor implementation of Verilog language and character display Chinese characters! ! Has been successfully compiled, you can directly use! ! !
verilog
- 无线通信用verilog代码，超全，可用来做基本设计-Verilog code for wireless communications, ultra wide, can be used for basic design
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
Verilog-Vending-Machine-_-georgeBlog_-A-blab-on-t
- using vending machine we can collect ice cream along with a change or can be fullfilled by any other subsequent cooldrinks
Verilog
- 在Verilog中有两种类型的赋值语句：连续赋值和过程赋值。赋值表达式由三个部分组成：左值、赋值运算符（=或<=）和右值。右值可以是任何类型的数据，包括net型和register型；但对连续赋值，左值必须是net类型的数据；而过程赋值，左值必须是register类型的数据。下面将作详细描述-There are two types in the Verilog assignment statement: continuous assignment and process assignment