搜索资源列表
aes__code_based_on_verilog
- AES核心代码,用verilog写的,可供参考-aes core code using verilog for learning
LED
- FPGA中实现led流水灯,通过Verilog语言编程,程序中调用了xilinx公司提供的时钟分频IP CORE-This file is to achiece led like water
asyn_fifo2
- 采用Verilog语言,使用FPGA内部IP核FIFO模块,实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
Lab1
- 嵌入式计算和源代码,主要是芯片的设计和开发, 用c语言和部分verilog-embedded system core design
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
PCI_top
- 这是PCI运动控制卡的核心代码,我的一个项目程序,很好用,verilog 语言编写。-This is a PCI motion control card core code, I have a project program, easy to use, verilog language.
pong_game
- pong游戏的verilog代码,只上传了核心模块的代码,其他模块包括vga驱动和ps2键盘解码-the core code of the pong game, other module include vga and ps2 keyboard driver
A
- 此为用verilog hdl编写的FPGAproject 其中A5+工程为带vga显示 分辨率600*800@60HZ 带字母显示(直接将ASCII码输入到寄存器中 窗口大小可调整);A1工程为软核处理器 可配合使用 实测功能强大-This is written in Verilog HDL FPGAproject the A5+ engineering with VGA display resolution 600*800@60HZ with letters display directly
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
8pic_MCU
- 8位MCUIP核的设计与应用(verilog IP核设计)PIC处理器 西安电子科技大学硬件工程师培训资料-Design and Application of 8 MCU IP cores (verilog IP core design) PIC processor Xi an University of Electronic Science and Technology Hardware Engineer training materials
fft_core_test
- 基于FPGA的FFT的IP核实现,有其详细源码,采用verilog语言编写,内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
DDR3_128M16bit_2Port64bit
- Xilinx spartan6 DDR3驱动,编程语言Verilog,基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
RAM
- 用verilog实现了IP核的使用,例化了一个RAM,用来进行读写操作,另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写
Buf_FiFo
- verilog 编写的FIFO,里边有IP核和控制模块,-verilog write FIFO, inside the IP core and control module,
ROM
- FPGArom的IP核使用及仿真,Verilog语言,非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
zhixinkeji
- 北京至芯科技FPGA的学习资料,从备战Quartus II安装到IIC通信协议,每一章都有Verilog代码并且可以实现仿真程序,非常好用,讲的很详细-Beijing Science and Technology FPGA to the core learning materials, preparing to install Quartus II IIC communication protocol, each chapter Verilog code and can achieve sim
ROM
- 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建,读写,调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
dfe_filter
- DEF算法的FIR滤波器verilog代码,内有乘法器IP核,可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)