搜索资源列表
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
DW8051_core
- 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
61EDA_C1910
- ARM9架构简单CORE实现，可以综合，有实现步骤和说明，Verilog代码编写-ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
Verilog
- 无线通信FPGA 一书中的verilog代码- verilog core
fft_2011_3_23(COMPLETE-FFT1024)
- VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE
UDP_Core
- 本人用verilog编写的UDP协议，经测试可用。-I am prepared to use verilog UDP protocol, the test is available.
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
dds
- 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
dma_0
- SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
can_latest.tar
- 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
8051core-Verilog
- 可以在FPGA上，实现80C51的软核，经过验证-In the FPGA to realize the soft-core 80C51, proven
core
- OpenOCD内部Jtag层核心代码。OpenOCD可以使用户通过C代码仿真模拟Verilog-core of OPENOCD s JTAG
mpci32-verilog
- 一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
Manchester-Encoding-Verilog
- THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR
openmsp430_latest.tar
- 开源的MSP430 Verilog源码，供学习使用-Open Source MSP430 Core verilog code, for studying.