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tutorial7
- spartan 3e-counter lcd vhdl code u can use ise 9.2
db
- fulladder made by me I hope it works, the only thing I need from your database is the V74160.rar, the vhdl code for the 4 bit bcd counter with asynchronious reset.. please help me thank you
fre
- 频率计的VHDL代码，实验课验证过的，能测量0-99999999hz的频率，并且超过上下限会报警。-Frequency counter in VHDL code, lab verified, can measure 0-99999999hz frequency, and over the limit will alarm.
adder
- It is VHDL code of 16 bit adder program, counter and IIR filter
lab3no1
- Design the behavioral type of VHDL code for a 4-bit binary up counter. Include an overflow output signal with your code.
New-Microsoft-Word-Document
- vhdl code for 3-bit binary counter
VHDLBasicExperimentSJTU
- 上海交大几个基础VHDL 实验的代码,包括分频器，计数器，七段计数器，状态机，锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
counter
- This source code for counter writing in VHDL using Proteus software-This is source code for counter writing in VHDL using Proteus software
geleima--10
- 格雷码计数器 vhdL实现 quartus编译通过-Gray code counter VHDL quartus compiled by
counter60
- 六十进制计数器的VHDL源程序代码，很实用-Six decimal counter VHDL source code, very useful
shuzixitongn
- VHDL代码 计数器 完成一分钟内的计数，到59清零，提供4个频率选择-VHDL code counter finished within one minute count to 59 cleared, 4 frequency selection
ADC_TLC549
- 实现ADC转换的VHDL代码，利用计数器分频产生1MHz的频率，在此频率下，读取八位的AD数据并存储供处理使用，根据实际需要转换成模拟电平。-ADC conversion of the VHDL code, the use of counter divider to generate a 1MHz frequency, frequency, read eight of the AD data and stored for processing, according to the actual n
up_down_cntr
- vhdl code for up down counter
VHDL-counter
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the c
counter
- scrambler code for VHDL
vhdl_for_lcd.txt
- VHDL code for LCD counter display
VHDL-counter
- The VHDL testbench Design, with source code and testbench in detail
six-digit-counter-with-tb
- VHDL source code of six digit counter with testbench,with comments included
cntm60v
- 基于VHDL的60进制计数器代码，可以实现六十进制计数-60 binary counter based on the VHDL code can be achieved sexagesimal counting
cpld_kit_test
- VHDL code to implement basic gates and counter,Flip=Flop,Registers using Xilinx Platform.