搜索资源列表
i2c_in_cpld
- 用CPLD实现I2C接口，可以移植到FPGA中-Achieved with the CPLD I2C interface can be ported to FPGA,
Verilogjiaocheng
- fpga/cpld verilog教程精彩-fpga/cpld verilog
fsh
- 这是我的毕业可用8位的LED显示，有小数点的。设计哦，可以用的。可供参考-VHDL-based digital frequency meter With the rapid development of electronic technology, FPGA/CPLD appear in its high-speed, high reliability, series parallel mode of outstanding merit widely used in the electronic
cpldfpga
- cpld 与 fpga的区别 详细的介绍了其主要不同特点-cpld and the difference between fpga
KP5509ADPsch
- 对于学习CPLD和FPGA，自己想画电路板，并学习VHDL硬件语言很有帮助-For learning CPLD and FPGA, they want to draw the circuit board, and learn helpful hardware language VHDL
FPGAandCPLDentry-leveldetailedstudymaterials
- fpga和cpld入门级详细的学习资料，内容很详细很全面。非常实用。-entry-level fpga and cpld detailed study information, the content is more comprehensive. Very useful.
yt7132_clock
- 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system
A-VHDL-Primer---Bhasker
- VHDL exaples project from CPLD or FPGA
VerilogHDL_Emample
- 其他说明： 文中实例基本都不依赖实际具体的硬件，可以在任何厂家任何系列的FPGA/CPLD下综合使用（如Altera等，只要资源充足），还可以利用Synoposy公司的工艺库影射到ASIC，完全可以当作软IPCore使用。 -Other notes: the text does not rely on practical and concrete examples of basic hardware, manufacturers of any series in any of the
VHDL-based-taxi-meter
- 本源码介绍了一种出租车计价器的设计方案，并且是基于VHDL语言，可以轻松在FPGA/CPLD上实现-This source presents a taxi meter design, and is based on the VHDL language, you can easily in the FPGA/CPLD to realize
MUXplus2
- Max+plusⅡ是Altera公司提供的FPGA/CPLD开发集成环境，Max+plusⅡ界面友好，使用便捷，被誉为业界最易用易学的EDA软件。本资源分七节内容详细的讲解了MUX+PLUSⅡ软件的操作及应用。-Altera Max+ plus Ⅱ is provided by FPGA/CPLD development integration environment, Max+ plus Ⅱ friendly interface and easy to use, known as the ED
CPLDFPGAprog
- vdhl programming notes for cpld and fpga
10-jinzhi-counter
- 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
15-jinzhi-counter
- 15进制计数器 每计数十五次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Fifth decimal counter 15 counts each have a carry, is the basis for vhdl programming procedures, programmable logic devices used in fpga cpld
Altera-FPGA_CPLD
- FPGA CPLD 高级篇 教你怎么编verilog-FPGA CPLD senior articles teach you how to compile verilog
CPLDMod2
- CCD 驱动控制程序 基于CPLD 多项执行-CCD drive control program is based on a number of FPGA implementation
FIR_filter
- Parallel FIR filter example. It is low-pass filter for CPLD or FPGA platforms. Project compiled and simulated in Modelsim
vgaverilog
- 本程序实现了基于FPGA/CPLD的VGA显示设计，简单易懂，可以输出8种颜色，即3位RGB颜色，共8种组合。连接FPGA的VGA口和液晶等显示器即可观察实验现象。-This procedure implemented based on FPGA/CPLD' s VGA display design, easy to understand, you can output 8 colors, the three RGB colors, a total of 8 combinations. FPGA
Linux-driver-development2
- 作者：华清远见嵌入式学院。《Linux设备驱动开发详解》（08&09年度畅销榜TOP50）第2章、驱动设计的硬件基础。本章讲解底层驱动工程师必备的硬件基础，给出了嵌入式系统硬件原理及分析方法的全景视图。2.1节讲解微控制器、微处理器、数字信号处理器以及应用于特定领域的处理器各自的特点。2.2节对嵌入式系统中所使用的各类存储器与CPU的接口、应用领域及特点进行了详细讲解。2.3节讲解常见的外设接口与总线的工作方式，包括串口、I2C、USB、以太网接口、ISA、PCI和cPCI等。嵌入式系统硬件电路