搜索资源列表
cpu
- 简单的cup程序，帮助初学者学习cpu工作流程，含有仿真波形-Cup simple procedures to help beginners learn cpu workflow, containing simulated waveform
IP_CORES
- IC内核的设计源码！其中包含MP3内核，CPU内核，I2C内核等多达式种IC设计的源码！-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
risc
- 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
CPU
- 本人主要是介绍CPU和运算器级联的程序，采用的是VHDL语言-I was to introduce the CPU and the main computing device cascade process, using the VHDL language
CPU
- 利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
cpu_lynn
- Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
cpu16
- Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog descr iption of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
uart
- 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
DDCA_HDL_Examples
- mpis-CPU的VHDL语言设计，也包含了很多课件和例子。-MPIS-CPU
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
CPU16
- 自己用VHDL写的16位的CPU，在学校的课程上通过了测试。-Own use VHDL to write a 16-bit CPU, in school curriculum passed the test.
cpu
- 用全加器设计8位运算器逻辑电路图 2、根据逻辑电路用 VHDL编程实现 3、调试编译通过后，仿真 -this file can help you learn the design of cpu
Microprogramcontroller
- 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
cpu-poc
- 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.
course-design-cpu-poc
- 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.
CPU
- 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
Exp6_SPI_AD_DA
- 用VHDL在SOPC试验箱中实现DA_AD转换，用ＶＨＤＬ硬件描述语言实现处理器CPU-With VHDL SOPC test box in DA_AD realization, with VHDL language processor CPU hardware descr iption
cpu
- 8位CISC模型计算机设计，包括加减法存储输出的运算-8-bit CISC model of computer design, including the addition and subtraction operations stored output
CPU-design
- 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
POC-Project
- 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.