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文件名称:DDCA_HDL_Examples

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    46.13kb
  • 已下载：
    0次
  • 提 供 者：
    xia****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

mpis-CPU的VHDL语言设计，也包含了很多课件和例子。-MPIS-CPU
相关搜索： cpu vhdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.1_sillyfunction.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.1_sillyfunction.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.10_tristate.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.10_tristate.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.12_bitswizzle.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.12_bitswizzle.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.13_example.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.13_example.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.14_mux8.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.15_mux4.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.15_mux4.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.16_mux2.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.16_mux2.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.17_mux2_8.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.17_mux2_8.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.18_flop.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.18_flop.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.19_flopr_async.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.19_flopr_async.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.19_flopr_sync.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.19_flopr_sync.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.2_inv.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.2_inv.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.20_flopenr.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.20_flopenr.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.21_sync.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.21_sync.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.22_latch.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.22_latch.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.23_inv.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.23_inv.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.24_fulladder.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.24_fulladder.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.25_sevenseg.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.25_sevenseg.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.26_decoder3_8.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.26_decoder3_8.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.27_priority.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.27_priority.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.28_priority_casez.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.29_fulladder.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.29_fulladder.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.3_gates.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.3_gates.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.3_gates_alt.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.30_syncbad.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.30_syncbad.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.31_divideby3fsm.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.31_divideby3fsm.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.32_patternMoore.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.32_patternMoore.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.33_patternMealy.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.33_patternMealy.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.34_mux_param.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.34_muxgeneric.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.35_decoder.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.35_decoder.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.36_andN.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.36_andN.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.37_testbench1.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.37_testbench1.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.38_testbench2.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.38_testbench2.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.39_testbench3.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.39_testbench3.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.4_and8.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.4_and8.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.5_mux2.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.5_mux2.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.6_mux4.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.6_mux4.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.7_fulladder.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/Ex4.7_fulladder.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/example.tv
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/numbertest.vhd
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/testbench_example_dut.v
DDCA_HDL_Examples/DDCA_Ch4_Examples_HDL/testbench_example_dut.vhd
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.3_comparators.v
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.3_comparators.vhd
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.4_multiplier.v
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.4_multiplier.vhd
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.5_counter.v
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.5_counter.vhd
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.6_shiftreg.v
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.6_shiftreg.vhd
DDCA_HDL_Examples/DDCA_Ch5_Examples_HDL/Ex5.7_ram.v
DDCA_HDL_Examples/D

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