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hard-wired-controllers
- 计算机组成原理课程综合设计 硬连线控制器的常规CPU设计 北京邮电大学-Integrated Principles of Computer Organization course design - conventional hardwired controller CPU design Beijing University of Posts
my_cpu
- 计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测-Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4
cpu
- 简易处理器要求，应用QUARTUS软件和模块化、层次化的设计方法进行设计， 对各模块进行必要的仿真验证。-Simple processor requirements, the application of QUARTUS software and modular, hierarchical design method for design, Simulation and verification are carried out for each module.
cpu666
- 简易CPU设计，包含10条指令，5个模块-Simple CPU design, contains 10 instructions, five modules
S16C57
- 8位RISC CPU 设计IP，包含了文档、代码、仿真环境等-8BIT RISC MCU implemention reference ip,include rtl code,simulation and document
OExp11-OwnMCPU
- 浙江大学计算机组成实验课工程代码，多周期CPU设计控制器实现。-Multi-cycle CPU design of the controller.
singleTcpu
- 单周期cpu设计，基于xilinx ISE环境设计，使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
prodesb
- 有是一个简单的cpu设计的开发过程！里面 有代码,和分析-There is a simple CPU design development process.
新建 Microsoft Word 文档
- CAN 接收器总共有 5 级接收 FIFO，在接收过程中，收到的报文将会依次在 5 级的输入 FIFO 中进行保存。CAN 中，5 个报文缓冲器在工作过程中通过转换被 交替映射到单片机的每个存储器区域内。RxBG（后台接收缓冲器）只与 MSCAN 相联系，前景接收缓冲器能够通过 CPU 寻址。(The CAN receiver has a total of 5 stages to receive the FIFO, and in the reception process, th
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
eetop.cn_RISC32 VHDL
- 根据vhdl设计的32位CPU具备加减 读写等标准功能(a 32-bit cpu based on VHDL designed with function of fundamental function of subtraction , addition, load and store .)
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
sdcc-src-2.9.0.tar
- sdcc是为51等小型嵌入式cpu设计的c语言编译器源码(sdcc to 51 other small-scale embedded cpu design c compiler sourecode)
p6_5
- buaa计算机组成P6程度的ISE源代码。设计思路与课件上的一致，供大家参考，切勿抄袭(BUAA computer makes up P6 degree ISE source code. Design ideas and courseware on the same, for your reference, do not plagiarize)
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)
cpu_2013
- 简化的16位的cpu的设计，有缓冲器，指令存储器，数据存储器等基本模块组成(The simplified 16 bit CPU design consists of a buffer, instruction memory, data memory and other basic modules)
CPU
- 针对硬件开发，采用VHDL编写 哈工大计算机设计与实践(Hardware development)
单片机电子时钟设计
- 单片微型计算机简称单片机，又称为微控制器，是将CPU、RAM、ROM、定时/计数器、I/O接口电路集成到一块电路芯片上构成的微型计算机。本次设计的系统由单片机系统、数码管显示系统、键盘、蜂鸣器等组成，通过按键来控制单片机实现数字时钟的时、分、秒显示，12、24制转换，设定时间、闹钟等不同功能，并通过P0口的输出在LED上显示。该设计具有结构简单、使用方便等特点。(As the single chip computer, also known as micro controller, CPU, R
mips16
- 来自openhec平台，完整的mips16cpu设计。未添加工程，需自己手动建立工程添加文件，仅供参考。(mips16 cpu.no vivado project.It's just for teaching.If you want to learn more about it, please search for OpenHec.)
实验九 计算机核心（CPU+RAM）的设计与实现
- 计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)