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PipelineSim
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PIPELINE
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PipelineCPU
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
x
- 某五级流水线CPU的设计原理图,含基本输入输出控制-traditional pipelined CPU design
PipelineSim
- 用verilog编写的简单流水线CPU,指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
liushuixianCPU
- VHDL 流水线CPU的设计,基于Quartus II平台-VHDL design of pipelined CPU based on Quartus II platform
RISC_CPU
- 一个32位流水线 CPU 设计, 含设计文档和模拟图。-A 32-bit pipelined CPU design, including design documentation and simulation in Fig.
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码,适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU,基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于,5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型,这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句,从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
CPUv1.6
- 简单的流水线CPU 课设做的 有实验报告 跟设计图-Simple pipelined CPU Lesson set up a lab report with design
piplelinecpu
- 流水线CPU,实现MIPS简单指令的运行,在XLINX实验板上运行-Pipelined CPU, MIPS simple instructions to achieve the operation, run in XLINX experimental board
Lab9-Forwarding-Unit
- CSCE2214课程设计,试验9源代码。实现流水线结构的MIPS CPU 16位。配有强大的Forwarding Unit.-CSCE2214 curriculum design, test 9 source code. Implement pipelined MIPS CPU 16 place. With a strong Forwarding Unit.
PipelineCPU
- 设计一个32位流水线MIPS微处理器,具体要求如下: 1. 至少运行下列MIPS32指令。 ①算术运算指令:ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令:AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令:SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令:BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令:J、JR。 ⑥数据传送指令:LW、SW
CUP
- 流水线cpu,简单的CPU,但是功能俱全-Pipeline cpu
pipeline_cmd
- 这是用Python实现的16位cup的代码 其中提供了流水线与分支预测的功能 如果你有在学习计算机原理或者体系结构的话,研究和实现这些源码对你的知识架构很与偶帮助-This archive File includes the code to simulate the 16bit cpu. We use Python to implement our design. In the CPU pipeline and branch estimate technique is added. If
pipeline10
- 用verilog实现嵌入式系统的处理器的五级流水线。-realizing the five stages of cpu in the embedded system with the verilog language
cpu_design
- FPGA MIPS架构CPU,五段流水线功能,ISE开发,verilog语言,可综合,模拟结果正确,内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
computer-composition
- Verilog在FPGA上实现多周期流水线带forwarding和hazard检测(如果你是学弟,为你着想,请不要直接copy)-Verilog on FPGA implementing a multi-cycled CPU with forwarding and hazard test
VHDLCode_8bitCPU
- 这是计算机组成原理的课程设计,将16位CPU改造成8位流水线CPU,AHDL语言,这是改造完成的源代码。-This is a computer composition principle of curriculum design, the 16-bit CPU transformed into eight pipeline CPU, AHDL language, which is the transformation was complete source code.