搜索资源列表
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
SRC
- 流水线CPU的verilog实现，包含id，if，ex，mem等部分的源码-an implementation of Pipelined CPU in verilog
CPU_Project_board
- CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）-5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce)
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Code1
- 拥有提前判断，和假设分支条件不满足的流水线CPU- Pipeline CPU with forwarding and predict-not-taken
pcpu_handle_mem
- Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
jiemr480
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性-Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU
1266318
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性-Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
Can_chaqacteristacs_bore
- 可以获得CPU的缓存大小,流水线数等等30多项CPU的特性(Can get the CPU cache size, number of lines and so on more than 30 characteristics of the CPU)
cpu2
- 这是在vivado平台上编写的多功能流水线cpu的实现，是我们课程实验的大作业(This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.)