搜索资源列表
lab_simulation
- verilog 开发的，模拟CPU流水线操作的工程设计。-verilog developed to simulate the engineering design of CPU pipelining.
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
MulticlockCPU.tar
- verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
LIP2321CORE_cpu_local_ram
- CPU Local RAM Verilog Module
rom_pld_top
- PC CPU 大廠 Intel 所使用的 Verilog code-Intel CPLD Verilog code
Leg8
- 待商业化的8位高速cpu芯片设计，verilog语言编译通过，ISE平台完成-To be commercial cpu 8-bit high-speed chip design, verilog language compiler, ISE platform to complete
Verilog_cpu-_example
- 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
risc8
- 基于verilog的8位risc-cpu源码，modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
SigCylCPU
- 单周期cpu的设计实现在VHDL中的verilog中实现。 -Design and implementation of single-cycle cpu in VHDL to implement the verilog.
MulCylCPU
- 多周期cpu在VHDL中的verilog实现-More cpu cycles in the verilog implementation in VHDL
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
mini_cpu_verilog
- 用verilog写的简单的CPU，有详细注释-Use verilog to write a simple CPU, with detailed notes
ece5742010hw9CPU
- 用verilog语言实现CPU， 其中包括几个不同的模块，每个模块中间由总线进行连接-implement the CPU using Verilog language, including the memory, controller,data path, the logic unit.
cpu_verilog_vhdl
- CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现，MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
single_cpu
- 单时钟CPU在XilinxISE 10.1的全代码，由Verilog语言描述-Single-cycle CPU in Verilog developed on XilinxISE 10.1
MIPSCPU
- 用verilog描述语言实现的MIPS32位单周期CPU。-Verilog descr iption language with the MIPS32-bit CPU.
cpu_fsm.tar
- cpu的verilog的不同状态的状态机实现程序编写-write or reset or read or delay of CPU by verilog