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TVerriRiscCPPh
- 这个文件中使用verilog hdl简单易懂懂的运用基本运算实现了微型的cpu设计开发过程 -Verilog hdl straightforward to understand the use of basic operations miniature cpu design and development process used in this document
mips_single
- 這是以verilog所撰寫的MIPS single CPU文件檔。可完成簡單的加減運算。 -This is the verilog are written in MIPS single CPU document file. To be completed by the simple addition and subtraction.
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier，可加到NiosII CPU之上，完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
mp2
- 用verilog 写的微程序多周期CPU.软件版本为10.1-Micro-program written in verilog. Multi-cycle CPU software version 10.1
PipelineSim
- 用verilog编写的简单流水线CPU，指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
LineEngine_tpf4
- Designing a Line Engine for CPU in verilog
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
SAYEH
- Verilog 数字系统设计---综合、测试平台与验证 .书中源程序-cpu in verilog descr iption. include C language source
demo_2012_2
- KD_CPU,8位实现基本功能的cpu，基于verilog-KD_CPU,8bit CPU with basic functions, base on verilog
Dragon-Heart_VERILOG.doc
- 神州龙芯cpu的verilog设计规范，本规范适用于下列三种 Verilog代码文件的编写：1）可综合逻辑部件；2）虚拟部件（Virtual Component--VC）；3）测试模块（testbenches）。-The verilog design specification of BLX cpu
code_VHDL
- 无流水无cache的cpu代码，基于verilog，CPU 芯片的主频是 15.3MHz,FPGA 器件的资源占用率为 28 -cpu code with no water nor cache
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
control_pipeline.zip
- Verilog components for a pipelined cpu simulation,Verilog components for a pipelined cpu simulation
SingleCycleCPU.zip
- A complete single cycle cpu written in verilog. (Including test modules),A complete single cycle cpu written in verilog. (Including test modules)
Multi
- A Complete Multicycle CPU Written in Verilog Lang.
para_serial
- 利用Verilog语言实现串并转换和并串转换，方便CPU和单片机之间通信 -Verilog to implement a serial-to-parallel conversion and parallel-to-serial conversion, to facilitate communication between the CPU and the microcontroller
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
DW8051
- dw8051 verilog 源代码，包括cpu的各个模块定义，实现。可综合IP软核-dw8051 verilog
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo