搜索资源列表
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
cpu
- Verilog代码，支持IO，中断的cpu实现。-Verilog code, support IO, interrupt cpu implementation.
cpu
- verilog 8 bit cpu working condition but need minor modification
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
CPU(4)
- 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
cpu-7-verilog
- 多周期cpu设计asadsdddasd-multi cpu design
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
cpu_verilog
- cpu的verilog描述的代码。比较适合初学者，-cpu verilog descr iption of the code. More suitable for beginners,
cpu
- 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
CPU
- 用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
Zet-1.3.1
- 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 int
mips
- mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
MCPU
- 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
hamming
- verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)
cputop
- cpu简单开发，利用verilog实现。 并进行下板实验(CPU is simply developed and implemented with Verilog. And carry out the experiment of the lower plate)