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靳远－源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
cpu16
- 一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
数字系统设计教程4_9
- vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
数字系统设计相关
- 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
jiyuVHDLdeIPheyanzheng
- 摘要 探讨了IP 核的验证与测试的方法及其和 VHDL语言在 IC 设计中的应用 并给出了其在RISC8 框架 CPU 核中的下载实例．-Abstract IP nuclear testing and certification of the method and its VHDL and in IC Design and Application given its RISC8 framework in the CPU core downloaded example.
addch1
- 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
mul6
- 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Behaviouralmodelofasimple8-bitCPU
- 个人认为几个比较实用的VHDL源码之二——Behavioural model of a simple 8-bit CPU-think of a few more practical VHDL source bis -- Behavioral mode l of a simple 8-bit CPU
MCUDesign
- 《Digital Logic And Microprocessor Design With VHDL》，CPU设计经典参考书-"Digital Logic And Microprocessor Design With VHDL, "CPU design classic reference books
cpu_VHDL
- vhdl 编写的cpu 代码, 详细说明了各个部分的功能及所有对应的代码，对cpu架构的学习和vhdl 编程有很大帮助(vhdl code for simple CPU)
FC? ????
- Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design mor
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- Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design mor
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- Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design mor
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- Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design mor
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- Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design mor
lu
- 16位MIPS指令集，VHDL实现，非常简单，非常粗暴(library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;)
cpu2
- 基于vhdl语言的cpu模拟，包含仿真，含所有器件(CPU containing simulation based on VHDL language)
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
ccsuemupc条件跳转(1)
- 设计一个模型机，具体设计要求如下： （1）设计指令系统，要求有取数指令、加法指令、跳转指令、停机指令等 （2）设计指令格式、微指令格式 、微程序 、时序电路 、数据通路，完成cpu的设计。 （3）利用模块化设计，分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等，最后进行系统的顶层设计，完成复杂模型机的设计与实现测试 （4）根据任务，完成主程序的设计，同时把主程序翻译成目标代码，写入主存，仿真下载测试。(Design a model machine, th