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文件名称:uart_design

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    2018-03-04
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UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
相关搜索: UART VHDL

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下载文件列表

文件名大小更新时间
uart_design 0 2018-01-19
uart_design\bote_creat.v 615 2017-07-25
uart_design\bote_creat.v.bak 615 2017-07-25
uart_design\bote_tb.v 244 2017-07-25
uart_design\bote_tb.v.bak 257 2017-07-25
uart_design\datamemory.v 322 2017-07-27
uart_design\datamemory.v.bak 325 2017-07-27
uart_design\History 0 2017-07-22
uart_design\History\bote_creat.~(1).v.Zip 469 2017-07-22
uart_design\History\bote_creat.~(2).v.Zip 471 2017-07-22
uart_design\History\bote_creat.~(3).v.Zip 471 2017-07-22
uart_design\History\uart_rx.~(1).v.Zip 728 2017-07-22
uart_design\History\uart_rx.~(2).v.Zip 732 2017-07-22
uart_design\History\uart_rx.~(3).v.Zip 732 2017-07-22
uart_design\History\uart_rx.~(4).v.Zip 732 2017-07-22
uart_design\History\uart_rx.~(5).v.Zip 739 2017-07-22
uart_design\History\uart_tb.~(1).v.Zip 252 2017-07-22
uart_design\History\uart_tb.~(10).v.Zip 494 2017-07-22
uart_design\History\uart_tb.~(11).v.Zip 494 2017-07-22
uart_design\History\uart_tb.~(12).v.Zip 495 2017-07-22
uart_design\History\uart_tb.~(13).v.Zip 501 2017-07-22
uart_design\History\uart_tb.~(14).v.Zip 501 2017-07-22
uart_design\History\uart_tb.~(15).v.Zip 501 2017-07-22
uart_design\History\uart_tb.~(16).v.Zip 501 2017-07-22
uart_design\History\uart_tb.~(17).v.Zip 502 2017-07-22
uart_design\History\uart_tb.~(18).v.Zip 502 2017-07-22
uart_design\History\uart_tb.~(2).v.Zip 252 2017-07-22
uart_design\History\uart_tb.~(3).v.Zip 342 2017-07-22
uart_design\History\uart_tb.~(4).v.Zip 372 2017-07-22
uart_design\History\uart_tb.~(5).v.Zip 375 2017-07-22
uart_design\History\uart_tb.~(6).v.Zip 375 2017-07-22
uart_design\History\uart_tb.~(7).v.Zip 375 2017-07-22
uart_design\History\uart_tb.~(8).v.Zip 394 2017-07-22
uart_design\History\uart_tb.~(9).v.Zip 425 2017-07-22
uart_design\History\uart_top.~(1).v.Zip 426 2017-07-22
uart_design\History\uart_top.~(2).v.Zip 447 2017-07-22
uart_design\History\uart_top.~(3).v.Zip 481 2017-07-22
uart_design\History\uart_top.~(4).v.Zip 481 2017-07-22
uart_design\History\uart_top.~(5).v.Zip 481 2017-07-22
uart_design\History\uart_top.~(6).v.Zip 481 2017-07-22
uart_design\History\uart_tx.~(1).v.Zip 376 2017-07-22
uart_design\History\uart_tx.~(10).v.Zip 762 2017-07-22
uart_design\History\uart_tx.~(11).v.Zip 788 2017-07-22
uart_design\History\uart_tx.~(2).v.Zip 380 2017-07-22
uart_design\History\uart_tx.~(3).v.Zip 491 2017-07-22
uart_design\History\uart_tx.~(4).v.Zip 496 2017-07-22
uart_design\History\uart_tx.~(5).v.Zip 492 2017-07-22
uart_design\History\uart_tx.~(6).v.Zip 600 2017-07-22
uart_design\History\uart_tx.~(7).v.Zip 595 2017-07-22
uart_design\History\uart_tx.~(8).v.Zip 756 2017-07-22
uart_design\History\uart_tx.~(9).v.Zip 756 2017-07-22
uart_design\tcl_stacktrace.txt 1682 2017-07-25
uart_design\transcript 2174 2018-01-18
uart_design\uart_cpu.v 2373 2017-07-27
uart_design\uart_cpu.v.bak 2369 2017-07-27
uart_design\uart_design.cr.mti 2142 2018-01-19
uart_design\uart_design.mpf 98039 2018-01-19
uart_design\uart_rx.v 2275 2017-07-26
uart_design\uart_rx.v.bak 2267 2017-07-26
uart_design\uart_tb.v 2344 2017-07-25
uart_design\uart_tb.v.bak 1548 2017-07-25
uart_design\uart_top.v 1321 2017-07-25
uart_design\uart_top.v.bak 1305 2017-07-25
uart_design\uart_tx.v 2189 2017-07-26
uart_design\uart_tx.v.bak 2191 2017-07-25
uart_design\uart_tx_tb.v 920 2017-07-25
uart_design\uart_tx_tb.v.bak 919 2017-07-25
uart_design\vish_stacktrace.vstf 254 2017-07-24
uart_design\vsim.wlf 40960 2018-01-19
uart_design\wave.do 1400 2017-07-27
uart_design\work 0 2018-01-19
uart_design\work\@_opt 0 2018-01-19
uart_design\work\@_opt1 0 2018-01-19
uart_design\work\@_opt1\_lib.qdb 49152 2018-01-19
uart_design\work\@_opt1\_lib1_0.qdb 32768 2018-01-19
uart_design\work\@_opt1\_lib1_0.qpg 0 2018-01-19
uart_design\work\@_opt1\_lib1_0.qtl 6015 2018-01-19
uart_design\work\@_opt1\_lib2_0.qdb 32768 2018-01-19
uart_design\work\@_opt1\_lib2_0.qpg 0 2018-01-19
uart_design\work\@_opt1\_lib2_0.qtl 6912 2018-01-19
uart_design\work\@_opt1\_lib3_0.qdb 32768 2018-01-19
uart_design\work\@_opt1\_lib3_0.qpg 0 2018-01-19
uart_design\work\@_opt1\_lib3_0.qtl 8972 2018-01-19
uart_design\work\@_opt1\_lib4_0.qdb 32768 2018-01-19
uart_design\work\@_opt1\_lib4_0.qpg 40960 2018-01-19
uart_design\work\@_opt1\_lib4_0.qtl 1520 2018-01-19
uart_design\work\@_opt\_lib.qdb 49152 2018-01-19
uart_design\work\@_opt\_lib1_0.qdb 32768 2018-01-19
uart_design\work\@_opt\_lib1_0.qpg 0 2018-01-19
uart_design\work\@_opt\_lib1_0.qtl 5886 2018-01-19
uart_design\work\@_opt\_lib2_0.qdb 32768 2018-01-19
uart_design\work\@_opt\_lib2_0.qpg 0 2018-01-19
uart_design\work\@_opt\_lib2_0.qtl 4673 2018-01-19
uart_design\work\@_opt\_lib3_0.qdb 32768 2018-01-19
uart_design\work\@_opt\_lib3_0.qpg 0 2018-01-19
uart_design\work\@_opt\_lib3_0.qtl 4324 2018-01-19
uart_design\work\@_opt\_lib4_0.qdb 32768 2018-01-19
uart_design\work\@_opt\_lib4_0.qpg 16384 2018-01-19
uart_design\work\@_opt\_lib4_0.qtl 6736 2018-01-19
uart_design\work\_info 3420 2018-01-19

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