搜索资源列表
ep2c35
- Cyclone 2 Altera PDF
EP3C120-LCD
- 应用verilog语言编写的在ALTERA-CYCLONE III 开发板1602上面显示字符-Application verilog language characters shown above in 1602
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
Pong
- We develop a Pong Game for Cyclone 2 Altera FPGA
procesador_2
- Processor in VHDL creating by us for Altera Cyclone II FPGA
DDR_CTRL
- DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
_6_key_led_with_debounce
- 键盘去抖，verilog控制LED发光，cyclone -键盘去抖，verilog控制LED发光，cyclone ii
mc8051_cyclone_nios
- mc8051 v1.4 oregano VHDL core for the Altera Cyclone Nios evaluation board.
ASP-upip-0.2
- web远控 ASP上线统计系统0.2 ASP上线系统默认用户密码: admin 123456 ASP上线系统必须使用IIS 5.0以上版本,且支持Asp脚本语言!不能使用小旋风等虚拟的IIS,否则无法接受数据-Web remote control ASP online statistical system 0.2 ASP on-line system default user password: admin 123456ASP on-line system must use the
OV7670initial
- ov7670硬件初始化代码，运行在alteral cyclone 2 fpga上-the hardware initializition of ov7670,running at cyclone 2 fpga platform
cycloneIII_3c25_start_my_first_fpga
- Q11 cyclone III 3c25 start my first fpga for cyclone 3 starter board altera
cyclone5_handbook
- Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements and the increasing bandwidth requirements for high-volume and cost-sensitive applications. The Cyclone V de
SDRAMPC7YC6008
- 基于cyclone ii系列的FPGA处理USB跟SDRAM通信系统，同时将lcd屏中的数据上传到PC中。-Cyclone ii series FPGA processing USB and SDRAM communication system, and the lcd screen in the data upload to PC.
led7219
- MAX7219驱动程序，应用于cyclone 1c12，电子设计大赛使用过的-MAX7219 driver, used in the cyclone 1c12 used by the Electronic Design Contest
ryy_uart_mult
- RS232串口驱动程序，应用于cyclone 1c12，发送和接收都有-RS232 serial port driver, used in the cyclone 1c12,including send and receive
spi
- Altera Cyclone SPI-slave vhdl module
AlteraFPGACycloneDemo1LampsSequencer
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
AlteraFPGACycloneDemo2DigitalCounter
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
AlteraFPGACycloneDemo3DigiatalCounter2
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
AlteraFPGACycloneDemo4-keyled1
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language