搜索资源列表
K4H511638D
- 512Mb D-die DDR SDRAM Specification
WS17
- weighing scale with 89s52, 24c08, PT6961 DDR, ADC 5532.
yuandaima
- 采用Delphi 6.0集成工具开发，语言object pascal，开发环境P4 1.8G+384 DDR +Windows 2000运行并测试成功；-Using Delphi 6.0 integration tool development, language, object pascal, development environment, P4 1.8G+384 DDR+ Windows 2000 running and testing success
spartan6_hdl
- Xilinx Spartan6 library reference.
bcm5354_wireless
- 这是我整理的老外在bbs中的一段讨论留言，其主要是关于BCM354 DDR的升级，这方面的资料非常的少，希望对给需要这方面资料的朋友有所帮助！-This is my finishing foreigners in the bbs in a discussion message, which is mainly on the BCM354 DDR upgrade information in this regard is very little hope to the needy this inf
ddrct_gen_xp_1_002_1
- ddrct_gen_xp_1_002_1，有关ddr控制的设计程序
ddrct_np_xm_3_005_1
- 有关ddr控制设计的问题，ddrct_np_xm_3_005_1.zip，非常值得参考！
ddrct_gen_o4_1_008_1
- 有关ddr设计的控制问题，ddrct_gen_o4_1_008_1.zip 非常有用
DanceDanceRevolutionWithHandGestureControl
- For the recognition of hand gestures, OpenCV and HandVu libraries are used to provide the functions of hand tracking and recognition. When a hand gesture is recognized, the result is sent to the DDR game through a network socket. Then, the DDR ga
ddr.ZIP
- 跳舞机小游戏,输入音乐文件，自生成节拍，跟提示进行游戏。-Game of dancing.
Dx0520soure
- WINCE下面的的DDRAW用户界面程序可以实现动画效果呀,是DDRAW界面编程的好例子-WINCE following the DDRAW user interface programs can achieve animation ah, is a good example of programming interface DDRAW
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
K3(Hi3611)GuideLine
- K3(Hi3611) 多媒体处理器研发指导手册(华为内部47页研发文档)-K3 (Hi3611) multimedia processor developed guidelines (Huawei R & D within the 47 documents)
DDR_Xilinx
- xilinx公司DDR控制ipxilinx公司DDR控制ip-xilinx公司DDR控制ip
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
DDR_rev0.2
- DDR memory interface for PNX8935, PNX8932, PNX8335, PNX8332
DDRSDRAM
- 用vdhl编写的DDR sdram控制器，采用模块化编写，条理清楚，注解详细，附有存储器的说明。-the ddr sdram controller base vhdl
ddr
- 跳舞机的源程序,觉得还不错，各位XDJM可以借鉴-Dance Dance Revolution source, that is not bad, can draw
sdram
- its the stuff to know about ddr sdram