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leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
cpu-leon3-altera-ep2s60-ddr
- 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！
ddr
- davincievm 6446 記憶體DDR撿測
ddr
- ddr控制器
DDR SDRAM控制器的VHDL代码已经测试
- DDR SDRAM控制器的VHDL代码已经测试
cyclone_ug_ddr_sdram
- ddr——sdram
DDR内存接口VC源程序IP核
- 很难看到的 DDR内存接口VC源程序IP核 ！ 各大公司用它卖钱的哦！
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
DDR_SDRAM.rar
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA,DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
DDR_SDRAM
- ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
mx27ads_x33
- i.mx27开发板的整套详细原理图，包括：DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface,
omap3530
- omap3530的datasheet，OMAP3530集成ARM+DSP+3D,ARM部分主频达到600MHZ，DSP采用430-MHz TMS320C64x+™ DSP Core，DDR可从128MB扩展到512M，尺寸基于7寸数字屏，主板由核心板和底板构成-omap3530 the datasheet, OMAP3530 integrates ARM+ DSP+3 D, ARM parts of speeds up to 600MHZ, DSP with 430-MHz TMS32
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
DDR2SDRAM
- 使用MIG工具生成DDR控制器的技术介绍-Using the MIG tool to generate the DDR Controller Technology
Hardware_and_Layout_Design_Considerations_for_DDR_
- DDR SDRAM接口的硬件和布线设计指南。DDR SDRAM的传输速度越来越高，对走线的要求也越来越高。-DDR SDRAM HARDWARE LAYOUT DESIGN
S3C6410_core_sch
- ok6410最新核心板最小系统原理图，包含mobile ddr， nandflash-ok6410 latest minimum system schematic core board, including mobile ddr, nandflash
DDR_SDRAM_controller
- ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t