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ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Twister_DDR_SDRAM_Board_Manual
- Twister DDR EP1C6Q240 FPGA 开发板 原理图,PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
mem-ctrl-rtl
- 实现对ddr的控制,可以在fpga的仿真环境下跑程序,并有testbench可以参考-implement ddr control
ddr_sdram_controller
- DDR SDRAM Controller design
DS-0050_OXE800SE_datasheet
- SATA NAS SOC,200MHz ARM926EJS核 SATA接口的NAS用处理器,集成USB2.0 HOST接口,Ethernet控制器,DDR SDRAM控制器,PCI HOST接口,可以扩展PCI外设。-SATA NAS SOC,NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller,USB2.0 HOST controller,Ethernet MAC controller,DDR SDRAM c
HY5DU121622CFP
- 64MB 512Mb, 16bit, DDR SDRAM MEMORY
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram
SDRAM
- 连接Nios II 和SDRAM的系统设计,DDR SDRAM设计及调试经验总结,MT48LC16M16资料。-failed to translate
S5PC100_UM_REV1.04
- Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 1
ddr
- 测试DDR内存,Linux下编译运行-Test Demos under CCS\tests\ddr
DDR_prj
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
DDRSDRAM_MT46V32M16TG
- ddr控制器 对DDR实现读写控制-ddr control
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
DDRdesigen.pdf
- DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
DDR
- HYB25025616的IP核,可直接用于microblaze的应用里,在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Magnetic
- 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰,还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号,像一些RF电路,PLL,振荡电路,含超高频存储器电路(DDR SDRAM,RAMBUS等)都需要在电源输入部分加磁珠,而电感是一种蓄能元件,用在LC振荡电路,中低频的滤波电路等,其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line frequency noise and interfere
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
ddr
- DM6446 ddr ccs 仿真器测试程序-DM6446 ddr program in CCS
DX-PHY
- ddr phy design spec and example-ddr phy design spec and example!!