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文件名称:DDRSDRAM_MT46V32M16TG

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  • 上传时间:
    2012-11-16
  • 文件大小:
    536.15kb
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ddr控制器 对DDR实现读写控制-ddr control
(系统自动生成,下载前可以参看下载内容)

下载文件列表

board_files/DDR_SDRAM/
board_files/DDR_SDRAM/Readme.txt
board_files/DDR_SDRAM/Syn/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/datasheet.txt
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/ddr.cpj
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/ddr.cdc
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/mem_interface_top.bit
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/mem_interface_top.edf
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/mem_interface_top.ucf
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/par.ise
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/par/Readme.txt
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/Readme.txt
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_addr_gen_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_cal_ctl_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_cal_top.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_clk_dcm.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_cmd_fsm_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_cmp_data_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_controller_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_controller_iobs_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_path_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_path_iobs_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_path_rst.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_read_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_read_controller_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_data_write_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_ddr1_dm_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_ddr1_test_bench_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_dqs_delay_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_fifo_0_wr_en_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_fifo_1_wr_en_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_infrastructure.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_infrastructure_iobs_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_infrastructure_top_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_iobs_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_lfsr32_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_main_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_parameters_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_RAM8D_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_RAM8D_1.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_rd_gray_cntr.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_s3_ddr_iob.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_s3_dqs_iob.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_tap_dly_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_top_0.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/rtl/mem_interface_top_wr_gray_cntr.vhd
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/ddr.v
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/ddr1_test_tb.v
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/ddr_parameters.vh
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/glbl.v
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/parameters.v
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/sim/readme.txt
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/mem_interface_top.lso
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/mem_interface_top.prj
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/mem_interface_top.sdc
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/mem_interface_top.xcf
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/mem_interface_top_synp.sdc
board_files/DDR_SDRAM/Syn/syn_vhd_bl4cl2/synth/script_synp.tcl
board_files/DDR_SDRAM/XST/
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/datasheet.txt
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/ddr.cpj
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/ddr.cdc
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/mem_interface_top.bit
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/mem_interface_top.ucf
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/Readme.txt
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/par/test.ise
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/Readme.txt
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/rtl/
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/rtl/mem_interface_top.v
board_files/DDR_SDRAM/XST/xst_vlog_bl2cl25/rtl/mem_interface_top_

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