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利用ISERDES和OSERDES实现高性能 .pdf
- FPGA DDR2设计资料
spartan6
- xilinx spartan-6 fpga原理图，包括电源部分，外接ddr2等功能 -xilinx spartan-6 fpga schematics, including power supply, external features such as ddr2
c_xapp702
- V4系列FPGA控制DDR2器件的中文介绍-V4 Series FPGA device in Chinese control of DDR2 Introduction
fpgaNDA
- 内容是基于FPGA的DDR2 的读写操作-FPGA-based DDR2 content is read and write operations
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
FPGA-SPARTAN3A-_DDR2
- 赛灵思FPGA SPARTAN3A 的DDR2接口设计-Xilinx FPGA SPARTAN3A the DDR2 interface design
DDR2_ctrl2
- DDR2_ctrl_fpga實現方法 內有FPGA使用簡介-FPGA design flow about DDR2
DDRCHv11
- Source code for ddr2 dram controller for BEEE
DDR2_test_Virtex5
- 针对于Virtex5 FPGA的DDR2读写测试的完整工程，2颗DDR2芯片的数据总线并接为32位，时钟200MHz-A full project for DDR2 test in Virtex5 FPGA board, with 32 bit data bus and 200MHz clock
DDR2SDRAM
- dm6446例程实验报告，详细的介绍了ddr2 sdram实验的过程-dm6446 report of the example
PCIeDDR2add
- PCIE-DDR2-双通道ADDA板主要用于AD数据的记录与回放。该板主要使用Xilinx公司的Virtex5 FPGA，通过PCIE IP核与主机通讯，存储系统包括DDR2 SDRAM和FLASH，为各种软件无线电技术的应用提供了一个非常强大的单插槽收发器解决方案。-PCIE-DDR2 dual-channel ADDA board is mainly used for the AD data recording and playback. The board Virtex5 the FPGA
FSM
- FPGA学习资料，新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
Spartan3-FPGA--DDR2-SDRAM
- FPGA学习资料，入门级掌握资料，ddr2内存-Spartan-3 FPGA 的 DDR2 SDRAM
PCI_Express_AD1_1
- pci-e高速ad高速采集，应用ddr2，fpga逻辑，verilog语言-pci-e ad-speed high-speed acquisition, application ddr2, fpga logic, verilog language
cdanpianji
- 红色飓风四代 altera DDR2 FPGA 开发 -FPGA development DDR2
DDR2-design-out-of-fpga
- FPGA外部的ddr2设计的相关学习资料-off-fpga，ddr design
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
vip_ex2
- 特权同学开发板上的例程，DDR2控制器集成与读写测试(The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests)
基于ov7670摄像头的VGA显示（FPGA）
- 系统上电后，先配置 OV7670 的寄存器，配置完后实时采集OV7670 的输出图像存储到DDR2 中，再实时的读出图像数据到 VGA 显示器中显示。代码采用verilog编写，适合开发者学习参考。