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clk_div
- ＦＰＧＡ Ｖｒｉｌｏｇ ＨＤＬ 分频器 输入３３ＭＨＺ ，输出１ＫＨＺ－５０ＨＺ-FPGA Vrilog HDL divider input 33MHZ, output 1KHZ-50HZ
songer
- 根据给出的乘法器逻辑原理图及其各模块的VHDL描述，学习利用数控分频器设计硬件乐曲演奏电路-According to the logic given multiplier module schematic and its VHDL descr iption, learning to use the numerical design of the hardware musical performances divider circuit
frequencydivider
- 计数器和分频器的PDF资料，供大家参考哈。希望对大家有用-Counter and frequency divider of the PDF information for your reference ha. Want to be useful to everyone
fre_devider_double
- 硬件中常用的偶分频电路的Vhdl源码，很有用-Even commonly used in hardware divider circuit Vhdl source code, useful
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
weisuijiganyixulie
- 本代码给出了伪随机感应序列的编写方法，练习熟练使用状态机-This code gives the state machine of the divider to prepare and practice skilled use of state machines
verilogDiv
- 高精度的二进制触发电路的verilog 源代码 结果低10位二进制数为小数 -binary divider designed with verilog
GCDcalulator
- its programs for finding the greatest comman divider
A9
- clock divider, has multiple versions of clock divider for the de2 board
3FSK.vhd
- 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
frequency_divider
- 分频器的编程思路为：32MHZ经过第1次分频变成1KHZ，再经过第2次分频变成100HZ，分别输出两次分频结果。-Divider of programming ideas for: 32MHZ after the first band to become a sub-sub-1KHZ, and then after the 2nd sub-band into a 100HZ, respectively, the results of the output frequency of the two
divider
- function [a_width-1 : 0] DWF_div_uns // Function to compute the unsigned quotient // synopsys map_to_operator DIV_UNS_OP // synopsys return_port_name QUOTIENT input [a_width-1 : 0] A input [b_width-1 : 0] B reg [a_width
Downloads
- clock divider in verilog for FPGA use
Architecture
- clock divider in XILINX
Clock_Divider_top
- Simple clock divider
C51_devider
- 用C51单片机实现分频，从外部输入一个分频系数，然后分频器的分频值会做相应的改变。-C51 Microcontroller with the divider from the external input a sub-frequency coefficients, and then the sub-frequency divider value changes accordingly.
counter_8050
- 本实验的功能为：10进制从80-50的计数器，2次/秒，这里的clk为50MHZ,一秒一次需要外加分频功能-The function of this experiment as follows: 10 binary counters from 80-50, 2 times/sec, where clk is 50MHZ, second function of a need for external divider
waterled_2group
- LED0--LED11,由LED0 LED1开始循环亮，2个灯为一组，每1秒换一组灯亮，这里用的时钟为50MHZ，因此需要外加一个分频器进行分频- LED0- LED11, from the beginning of the loop LED0 LED1 light, two lights as a group, every 1 second for a group of lights, where the clock used for 50MHZ, plus a divider so the
examples
- 分频时序逻辑电路 的设计 书上的题目 自己编写的程序 希望大家共同交流-Divider sequential logic circuits ok hrllo
clk_divide
- 实现了一个通用分频器，可以实现任何分频的程序-To achieve a common divider, can achieve any frequency of the procedure