搜索资源列表
backtracksrc
- Code for top down parser in C-Code for top down parser in C++
systemtestask
- 数字下变频的matlab仿真源程序，自动生产图形-Digital Down Converter，matlab source
wddc_module
- 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
Register
- -- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data in
UpDownCounter
- an up down counter in verilog
1
- 自上而下的语法分析器，实验内容之一，利用分析表、分析栈和总控程序对源程序进行自上而下的语法分析测试； -Top-down parser, one of the experiment, the use of analytical tables, analysis of the total stack and source code control procedures for testing top-down parsing
UP.DOWN.HEX.COUNTER
- Up down counter for microchip ASM code tested
ddc
- 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a
count-down
- 倒计时程序，按指定的时间，倒计时，时间到程序退出-count-down
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
Solutions_to_book
- SOLUTION MANUAL:" Computer Networking: A Top-Down Approach Featuring the Internet"2ND EDITION Solutions to Review Questions and Problems
AutoShutDo1721923192004
- This app will auto shut down your win xp computer by setting the time.
Chess
- Chinese chess, down load now
ComputerNetworking
- Computer Networking A Top-Down Approach Featuring the Internet
fg-menu
- javascr ipt multi level drop down menu with fade transition effects. Great for websites. User friendly and completey editable design.
FIR_TEST
- 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块，并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we des
tes_amp_80_0314
- 基于dsp builder的数字下变频器，IP核做的-digital down converter,degigned in matlab
timing_recovery
- 我对一个输入调制信号：采样率FS=1200K，中心频率F0=300K，带宽300K。输入信号为一个[样点数,2]的矩阵,即I,Q两路. 进行频谱搬移，分为I，Q分量两路进行矢量乘法，NCO的设置为FC=300K，t=样点数乘以1/FS， 乘完以后我的频谱上显示竟然信号带宽增加了300K，但是中心频率没有改变，请问各位朋友是哪儿出了问题？谢谢您的阅读和意见-Digital Down Converter for matlab realized, certain design speci
digital_down_convertation
- 我对一个输入调制信号：采样率FS=1200K，中心频率F0=300K，带宽300K。输入信号为一个[样点数,2]的矩阵,即I,Q两路. 进行频谱搬移，分为I，Q分量两路进行矢量乘法，NCO的设置为FC=300K，t=样点数乘以1/FS， 乘完以后我的频谱上显示竟然信号带宽增加了300K，但是中心频率没有改变，请问各位朋友是哪儿出了问题？谢谢您的阅读和意见-Digital Down Converter for matlab realized, certain design speci
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga