搜索资源列表
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
fifo
- 计算机操作系统中的页面置换算法源程序，包括fifo，lru，opt等，用vc编写-computer operating system replacement pages algorithm source code, including fifo, lru, opt. prepared using vc
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
CCD.rar
- CCD数字相机的全代码，DMA方式读取FPGA，FIFO送入计算机，网口跑UDP协议,CCD digital camera the entire code, DMA mode to read FPGA, FIFO into the computer, I run UDP network protocol
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
FX2_Slave_FIFO
- cy68013的从FIFO方式的通信源代码-cy68013 from the FIFO mode of communication source code
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
FIFO-verilog
- 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
A7125-Reference-code
- A7125低功耗低成本无线音频模块收发程序，调试通过！-A7125 low-power low-cost wireless audio transceiver module program debugging through!
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
88fifovhdl
- 88位进出缓冲器8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-88 out of 8* 8-bit buffer fifo data buffer vhdl source Bianle Ge 8* 8-bit data buffer fifo vhdl source code is compiled through quartusII4.2 successful progra
DSP_2812_SCI_232
- DSP2812串口通信编程，利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
FIFO
- fifo程序代码，程序编写，测试仿真图形，方便，比较实用-fifo code, programming, testing, simulation graphics, convenient and more practical
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
FIFO
- 提供的是页面置换算法中最简单的先进先出策略的java代码实现(The Java code implementation of the simplest FIFO policy in the page replacement algorithm is provided)
FIFO
- 简单fifo填入和读取的代码，供大家参考(simple demo code of FIFO)
fifo
- 基于verilog HDL的fifo设计与测试，包含设计与测试代码，以及简单的makefile编写。整个平台是基于linux操作，仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)