搜索资源列表
VHDL
- 滤波器 VHDL 应用VHDL基于FPGA设计FIR滤波器-Application of VHDL-based FPGA VHDL filter FIR filter design
da
- FIR滤波器利用串行DA算法实现16阶的，直接可用 ，用VHDL编程-Serial DA FIR filter algorithm using 16 bands, directly available, VHDL programming
CCD
- 本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
LinPF
- This a VHDL module that implements linear prediction filter based on NLMS (normalized least mean square). The module takes complex signal as input and output comlex signal (real and imaginary). Tap size is 4, bit precision is set to 12 bits.-This i
LinPF_RLS
- VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
CIC
- Efficient CIC filter Implementation using VHDL
FIR
- 本程序实现了FIR滤波器，使用了全并行的分布式DA算法，附有仿真波形。-FIR filter with DA
CIC_filter
- CIC滤波器的原理及FPGA实现 里面有我收集的各种关于CIC滤波器的FPGA 实现的文章及源码-CIC filter FPGA realization of the principle and there are a variety of my collection on the CIC filter FPGA implementation and the source article
3_3_mean_diltter(ALU)
- 3*3均值滤波的VHDL语言实现的工程，对红外图像进行有效的去噪处理。这是其中的ALU模块，专门用来测试其延迟状况的模块。-3* 3 mean filter VHDL language works effectively on the infrared image denoising. This is one of the ALU module, designed to test the status of the module delay.
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
mdf-code-4m-net
- median filter algorithm , VHDL code
mdf-code-xilinx
- median filter code in VHDl
mdf-arch2
- median filter algorthm
1002
- median filter algorithm help
med01-165
- median filter details
FIR-lv-bo-code
- 此代码为FIR滤波器的设计源码，并对其代码做了相应的改进，综合仿真结果成功-This code source code for the FIR filter design, and the code does a corresponding improvement, integrated simulation results successfully
17jieFIR
- 17阶FIR滤波器VHDL代码及说明文档-17-order FIR filter VHDL code and documentation
VHDL_TipsTricks
- tips to design fir filter step by step
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and