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CIC.rar
- CIC梳状滤波器verilog源码，包括积分器，下抽级以及梳状滤波器三个部分。,CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
18a
- 匹配滤波器设计，VERILOG实现的，比较好的哦-Matched filter design, VERILOG implementation, and better oh
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
FIR
- FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
cic
- 五阶CIC梳状积分滤波器，可以综合，非常有参考价值-Fifth-order CIC points comb filter, can be integrated and very useful
IIRfilterFPGA
- 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules
medianfilter
- 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
daima
- fir滤波器的代码实现，最好使用quartus ii开发工具-Fir filter code realization, had better use quartus ii development tools
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
interpolator
- 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现-Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
digital_filter
- 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
cvery.comdel7535899835
- 学生成绩管理 实现成绩的查询 录入多个公司的JAVA面试试题，供 ·模式识别matlab工具箱,包括SV ·文件类型：Visual FoxPro 人 ·struts2.0得例子,主要是实现s ·一个C#多线程的例子。 ·卡尔曼滤波器matlab源代码。 ·很不错的vhdl学习实例 几十 ·原版的FAT32手册,E文差的同志 ·常见的JAva面试试题，平时可 ·一个小型C语言编译器 -Student performance managem
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
Fir-40ntap-4order
- Fir filter with 40tap, 4 order