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median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
butterfly2
- This VHDL code for butterfly filter banks-This is VHDL code for butterfly filter banks
Verilog
- 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
MatchFilter
- VHDL语言实现8路并行输入，8路并行输出，直接序列扩频接收机的高速匹配滤波。 -VHDL language to achieve 8-channel parallel input, 8-channel parallel output, high-speed direct-sequence spread spectrum matched filter receiver.
Desktop
- DDS数字频率合成DDS由相位累加器、正弦查找表、D／A转换器和低通滤波器组成 -DDS DDS DDS from the phase accumulator, sine look-up tables, D/A converter and low-pass filter composed of
fir1
- this file consists of simple FIR filter designed with the fixed coefficients
iir
- IIR50HZ的数字陷波器的FPGA实现-IIR50HZ digital notch filter implementation in FPGA
PN_code_capture_and_tracing
- 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
fir_9222_sopc
- 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
IIR
- 实验说明： 本次实验实现一个IIR滤波器，并在ISE里面仿真。 project目录里面是工程-Experiment descr iption: this experiment to achieve an IIR filter, and the ISE inside the simulation. \ rtl directory which is the source file \ project directory which is the project
2046matchedfilter
- 2046点匹配滤波器，附带C/A码生成模块一个-2046 points, matched filter, with C/A code generation module 1
83390078DDS
- DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a
- 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础 上，采用超高速
hanning
- Hanning filter implemented in VHDL
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
VHDLonfir
- FIR滤波器在VHDL中使用(顺序)PROCESS声明或者是加法器和乘法器的“组件 实例”来实现-FIR filter in VHDL use (in order) PROCESS statement or the adder and the multiplier " component instance" to achieve the
5_3
- 53整数小波滤波，编译已经成功，仿真也已经通过，是网上着的资料-53 integer wavelet filter, has been successfully compiled, the simulation has also been adopted, is online with information
fir_filter
- 实现滤波器的功能，有限冲激响应（FIR）数字滤波器和无限冲激响应（IIR）数字滤波器广泛应用于数字信号处理系统中。IIR数字滤波器方便简单，但它相位的非线性，要求采用全通网络进行相位校正，且稳定性难以保障。FIR滤波器具有很好的线性相位特性，使得它越来越受到广泛的重视。-Realize the filter function, finite impulse response (FIR) digital filters and infinite impulse response (IIR) dig
fir_filter
- 该数字滤波器通过结合matlab和vhdl来实现低通fir数字滤波器功能-The digital filter through a combination of matlab and vhdl to achieve low-pass digital filter function fir