搜索资源列表
filter-vhdl-code
- filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
MyFilter.rar
- FPGA实现数字滤波器，用VHDL语言实现的直接1型FIR滤波器，具有较好的参考价值。,FPGA realization of digital filters using VHDL language to achieve the direct FIR filter type 1, has a good reference value.
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
FIR
- FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
FIR_VHDL
- FIR滤波器的VHDL代码,可以修改冲击函数的值-FIR filter VHDL code can modify the impact of the value function
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
Fir-40ntap-4order
- Fir filter with 40tap, 4 order
coeff_rom_1_6
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
coeff_rom_2_5
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
FIR
- 基于FPGA的FIR滤波器实现，含全部不源代码-FPGA-based FIR filter, including all non-source code
FPGAFIR
- FPGA-based high-order FIR filter design
beta
- Fir verilog code implemented to find out the output of fir filter
FIR_filters_Xilinx
- FIR filter design method using Xilinx FPGA platform.
fir
- 利用VHDL语言，设计了一个11阶的FIR滤波器。简单易懂-The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p
fir_liujiao
- 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
FIR
- fir filter design using vhdl codes
fir-c2h
- 基于fpga的fir滤波器的设计 非常好，谢谢大家分享-fir filter design base on fpga it is very good