搜索资源列表
VerilogUart
- UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
CoreUartTest
- Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
ASKmod1
- ASK调制信号产生，来源于《无线通信FPGA设计田耘》-ASK modulation signal generation, with some reference value, the Tian Yun wireless communication FPGA design
DDS
- 基于FPGA完成2001年电子设计竞赛直接数字频率合成器，有FPGA部分、MSP430程序以及相互通信的程序，完成题目全部要求-FPGA-based Electronic Design Competition 2001 complete direct digital frequency synthesizer, there is part of the program FPGA, MSP430 procedures and communicate with each other, to comp
socket_apps
- FPGA与pc socket模式下通信 所用的板子为ml605_AxiEth_8Kb_Cache-FPGA and socket PC mode of communication used by the board for the ml605_AxiEth_8Kb_Cache
raw_apps
- FPGA与pc raw模式下通信 所用的板子为ml605_AxiEth_8Kb_Cache-FPGA and raw PC mode of communication used by the board for the ml605_AxiEth_8Kb_Cache
socket_apps
- FPGA与pc socket模式下通信 所用的板子为sp605_AxiEth_8kb_Cache-FPGA and socket PC mode of communication used by the board for the sp605_AxiEth_8kb_Cache
raw_apps
- FPGA与pc raw模式下通信 所用的板子为sp605_AxiEth_8kb_Cache-FPGA and raw PC mode of communication used by the board for the sp605_AxiEth_8kb_Cache
raw_apps
- FPGA与pc socket模式下通信 所用的板子为AC701_AxiEth_100MHZ_32kb-FPGA and socket PC mode of communication used by the board for the AC701_AxiEth_100MHZ_32kb
socket_apps
- FPGA与pc socket模式下通信 所用的板子为AC701_AxiEth_100MHZ_32kb-FPGA and socket PC mode of communication used by the board for the AC701_AxiEth_100MHZ_32kb
RS485
- FPGA/CPLD实现RS485通信协议，在Quartus ii平台上进行Verilog编程仿真-FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
gpmc_fpga
- 实现arm与fpga之间通过gpmc总线通信-the device of fpga
receive_uart
- fpga串口通信，接收模块程序.verilog语言编写-fpga serial communication, receiving module program
6_USB_to_SDHC_Lab
- 基于altera公司MAX10型FPGA的usb至sdhc通信的调试程序-Altera company based debugger MAX 10 type of FPGA to sdhc usb communication
8_MIPI_to_HDMI_Terasic
- 基于altera公司MAX10型FPGA的mipi至hdmi通信的调试程序-Altera company based debugger type of FPGA MAX 10 spi to hdmi communication
RS485
- verilog开发FPGA，实现RS485串口通信-RS485 driver for FPGA
Dual-RAM
- DSP EMIF双口RAM和FPGA实现高速通信-DSP EMIF dual-port RAM and FPGA to achieve high-speed communications
fpga_spi
- 利用FPGA实现spi通信协议,通过modelsim仿真-Using FPGA to achieve spi communication protocol
uart_lcd_display_XUP
- Uart串口通信程序，PC机向FPGA的串口发送数据，FPGA的串口收到数据后回传到PC机，同时显示在lcd屏。-Uart serial communication program: The serial port of PC sends data to the FPGA. After the serial port of FPGA receives the data, FPGA sends the received data back to the PC, simultaneously dis