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文件名称:CoreUartTest

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-09-21
  • 文件大小：
    817.47kb
  • 已下载：
    2次
  • 提 供 者：
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CoreUartTest/component/Actel/DirectCore/COREUART/5.5.101/COREUART.cxf
CoreUartTest/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.cxf
CoreUartTest/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
CoreUartTest/component/work/DESIGN_IO/DESIGN_IO.cxf
CoreUartTest/component/work/DESIGN_IO/DESIGN_IO.sdb
CoreUartTest/component/work/uart1/uart1.cxf
CoreUartTest/component/work/uart1/uart1.sdb
CoreUartTest/component/work/uart1/uart1.v
CoreUartTest/component/work/uart1/uart1_0/coreparameters.v
CoreUartTest/component/work/uart1/uart1_0/mti/scripts/wave_vlog.do
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/core/Clock_gen.v
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/core/CoreUART.v
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/core/fifo_256x8_pa3e.v
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/core/Rx_async.v
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/core/Tx_async.v
CoreUartTest/component/work/uart1/uart1_0/rtl/vlog/test/user/testbnch.v
CoreUartTest/component/work/uart1/uart1_0/uart1_uart1_0_COREUART.cxf
CoreUartTest/component/work/uart1/uart1_manifest.txt
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/coreparameters.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/mti/scripts/wave_vlog.do
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/core/Clock_gen.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/core/CoreUART.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/core/fifo_256x8_pa3e.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/core/Rx_async.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/core/Tx_async.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/rtl/vlog/test/user/testbnch.v
CoreUartTest/component/work/uart_SmartDesign/COREUART_0/uart_SmartDesign_COREUART_0_COREUART.cxf
CoreUartTest/component/work/uart_SmartDesign/datasheet.xsl
CoreUartTest/component/work/uart_SmartDesign/drcss.xsl
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign.cxf
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign.sdb
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign.v
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign_DataSheet.xml
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign_DRC.xml
CoreUartTest/component/work/uart_SmartDesign/uart_SmartDesign_manifest.txt
CoreUartTest/CoreUartTest.prjx
CoreUartTest/designer/impl1/run_designer_tool.log
CoreUartTest/designer/impl1/run_designer_tool.tcl
CoreUartTest/designer/impl1/run_pinrpt.tcl
CoreUartTest/designer/impl1/uart_SmartDesign.adb
CoreUartTest/designer/impl1/uart_SmartDesign.dtf/verify.log
CoreUartTest/designer/impl1/uart_SmartDesign.ide_des
CoreUartTest/designer/impl1/uart_SmartDesign.pdb
CoreUartTest/designer/impl1/uart_SmartDesign.pdb.depends
CoreUartTest/designer/impl1/uart_SmartDesign.tcl
CoreUartTest/designer/impl1/uart_SmartDesign_compile_log.rpt
CoreUartTest/designer/impl1/uart_SmartDesign_compile_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_fp/$$FlashPro_97574.L$$
CoreUartTest/designer/impl1/uart_SmartDesign_fp/projectData/uart_SmartDesign.pdb
CoreUartTest/designer/impl1/uart_SmartDesign_fp/uart_SmartDesign.pro
CoreUartTest/designer/impl1/uart_SmartDesign_fp.tcl
CoreUartTest/designer/impl1/uart_SmartDesign_globalnet_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_globalusage_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_iobank_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_maxdelay_timingviolations_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_maxdelay_timing_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_mindelay_timingviolations_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_mindelay_timing_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_placeroute_log.rpt
CoreUartTest/designer/impl1/uart_SmartDesign_place_and_route_report.txt
CoreUartTest/designer/impl1/uart_SmartDesign_prgdata_log.rpt
CoreUartTest/designer/impl1/uart_SmartDesign_report_pin_byname.txt
CoreUartTest/designer/impl1/uart_SmartDesign_report_pin_bynumber.txt
CoreUartTest/designer/impl1/uart_SmartDesign_verifytiming_log.rpt
CoreUartTest/simulation/modelsim.ini
CoreUartTest/simulation/modelsim.ini.sav
CoreUartTest/smartgen/DESIGN_FIRMWARE_work.ixf
CoreUartTest/smartgen/DESIGN_IO_work.ixf
CoreUartTest/smartgen/pllcore1/pllcore1.cxf
CoreUartTest/smartgen/pllcore1/pllcore1.gen
CoreUartTest/smartgen/pllcore1/pllcore1.log
CoreUartTest/smartgen/pllcore1/pllcore1.v
CoreUartTest/smartgen/pllcore1_work.ixf
CoreUartTest/smartgen/smartgen.aws
CoreUartTest/smartgen/uart_SmartDesign_work.ixf
CoreUartTest/synthesis/backup/uart_SmartDesign.srr
CoreUartTest/synthesis/dm/uart_SmartDesign_comp.xdm
CoreUartTest/synthesis/run_options.txt
CoreUartTest/synthesis/scratchproject.prs
CoreUartTest/synthesis/synlog/map.srr.rptmap
CoreUartTest/synthesis/synlog/pre_map.srr.rptmap
CoreUartTest/synthesis/synlog/report/uart_SmartDesign_compiler_notes.txt
CoreUartTest/synthesis/synlog/report/uart_SmartDesign_compiler_runstatus.xml
CoreUartTest/synthesis/synlog/report/uart_SmartDesign_compiler

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