搜索资源列表
clock
- fpga数字时钟 调试 报警 ,fpga用比较少的代码加上更多的功能-digital clock debugging report to the police
plj.FPGA
- 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号,被测方波为信号发生器产生的方波信号,显示电路由TTL芯片及七段数码管组成的电路,自校正输出由CPLD输出已知频率的测试方波信号,可将其输入至测试端口,进行系统精度校正。 -The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test
clock
- FPGA编程,用Verilog语言实现数字钟功能-The FPGA programming, the function for digital clock with Verilog language
clock-for-nios
- 基于niosⅡ的数字钟设计,适用于多种FPGA的开发板,修改管脚可移植。-NiosⅡ digital clock design is based on, for a variety of FPGA development board, modify pin portable.
clk_gen
- 常见的FPGA 时钟模块代码实例,仅供大家参考-FPGA clock RTL
CLOCK-CODE-VHDL
- VHDL源码程序,功能完整的时钟电路代码-using ALTERA s FPGA design, QUARTUS software development platform.VHDL CARD,
FPGA
- 数字钟的VHDL语言程序,包含了好几个模块,是毕业设计的优秀程序,值得下载!-VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!
XAPP879---PLL
- 基于FPGA的PLL锁相环设计资料,能给FPGA提供稳定的工作时钟,很好的资源啊!-FPGA based PLL to design information, give FPGA clock to provide a stable work, good resource ah!
FPGA-digital-clock-and-stopwatch
- 这是一个FPGA数字时钟及秒表的源程序,具有调试功能,适合fpga爱好者借鉴。-This is source code about FPGA,including digital clock and stopwatch,and you can use it according to your need.
fpga
- 用FPGA实现的多功能数字钟时,可以定闹钟,校对时间。-When implemented in an FPGA multifunction digital clock, you can set the alarm, set the time.
clock
- 程序主要对是信号波形取反,可以用来测试FPGA芯片的引脚功能是否正常。-Signal waveform inversion,can be used to test the FPGA chip pin function.
Digital-clock
- 基于FPGA实现数码管数字时钟功能 使用芯片为EP2C8Q208C8N,使用数码管显示数字时钟,使用Verilog语言编程,本例子有工程文件、仿真、波形,经过测试可以使用。-Based on FPGA digital tube digital clock function uses chip EP2C8Q208C8N, use digital display digital clock, using Verilog language programming, the present exam
dds_clk
- FPGA工作时钟位50MHz,通过引出FPGA时钟信号,供给外部DDS模块使用。-FPGA clock work bit 50MHz, led by FPGA clock signal supplied to the external DDS module.
clock-with-alarm-and-timer
- FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!-FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!
4.实验四 硬件综合实验
- 实验目的: 熟悉ISE8.2开发环境,掌握工程的生成方法; 熟悉SEED-XDTK_V4实验环境; 了解LCD的HDL实现; 了解Memory模块的使用。 实验内容: FPGA的memory模块的生成及例化; 系统时钟设计; LCD点亮。(Experimental purpose: Familiar with ISE8.2 development environment, master the method of Engineering generation;
数字钟(8)
- 数字钟(总)整点报时,8位数码管显示。VHDL语言设计。。。。(Digital clock (total) the whole point timekeeping, 8 digital display. VHDL language design....)
RTC
- Verilog语言编写的IIC读取RTC实时时钟程序(real time clock based on FPGA)
Digital_clock
- 教程 基于FPGA的智能闹钟,控制NOKIA5110(Intelligent alarm clock based on FPGA, control N O K I A 5110)
至简设计法--闹钟
- 闹钟 工程说明 本工程包括矩阵键盘和数码管显示模块,共同实现一个带有闹钟功能、可设置时间的数字时钟。 案例补充说明 我们通过建立四个清晰直观的模块(数码管显示模块,矩阵键盘扫描模块,时钟计数模块,闹钟设定模块),以及建立完善的信号列表和运用verilog语言编写简洁流畅的代码,实现电子闹钟时、分、秒计时以及设置、修改、重置等功能。(alarm clock Engineering descr iption This project includes matrix keyboard and di
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)