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CLOCK
- 基于FPGA的多功能电子时钟的设计很经典的哦
基于FPGA的直接数字合成器设计
- 1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use
基于fpga的多功能电子钟的设计
- 基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊,FPGA-based multi-functional electronic clock design to use would like to help everyone ah
LPT.rar
- 实现开漏输出的并口,支持3.3V或5V,支持FPGA 的PS 配置功能。8位配置数据 自动移位输出,输入时钟24MHz,产生1MHz配置时钟。8位CPU数据总线接口, 11位地址总线。支持IO 的置位清除功能。,The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit config
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码,可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
FPGA实现多功能闹钟
- FPGA实现多功能闹钟,有电子钟、秒表、定时器、电子琴功能-FPGA realization of multi-function alarm clock, which can function as a clock, a stopwatch, a timer,and a piano.
FPGA-global-clk-design-
- FPGA的全局时钟应该是从晶振分出来的,最原始的频率。其他需要的各种频率都是在这个基础上利用PLL或者其他分频手段得到的;因为全局时钟需要驱动很多模块,所以全局时钟引脚需要有很大的驱动能力,FPGA一般都有一些专门的引脚用于作为全局时钟用,他们的驱动能力比较强-FPGA' s global clock should be divided out from the crystal, the frequency of the most original. Other needs of the
FPGA-digital-clock-design
- 运用顶层设计思路设计好各个底层文件(VHDL代码),对各个底层文件进行功能仿真;采用原理图或者文本方法来实现顶层文件的设计,对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后,把顶层文件下载到实验箱的FPGA里边去,验证电路功能是否正确。具体时间用6位数码管来显示,具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of variou
fenpin
- FPGA的一个分频程序,FPGA时钟频率问100MHz,进行100000000分频。-A sub-frequency program FPGA, FPGA clock frequency asked 100MHz, for 100 million frequency.
5B6B
- FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or b
DCM
- ISE实现DCM组建例化,得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
rs232
- fpga的串口读写程序,经硬件测试成功,波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
clk_vhdl
- Quartus II工程压缩文件,是一个典型的基于FPGA的数字钟工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
Senior-Advanced-FPGA-design
- FPGA设计高级进阶,讲述了流水线,乒乓操作,异步时钟域处理,状态机等内容-Senior Advanced FPGA design, about the line, ping-pong operation, asynchronous clock domain processing, state machine, etc.
UART
- 使用Quartus ii软件,编程语言为Verilog语言,实现UART通信协议,FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时钟频率比外部时钟更高,时钟延迟和时钟偏移最小,减小或调整时钟
DCM
- xilinx SP605开发板的DCM模块验证程序,coreGen工具生成DCM核,由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
EDA
- 数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL
sjcj
- 通过ADC0809对模拟信号进行采样,然后将转换好的8位数据迅速转存到FPGA内部存储器中,同时增加一个锯齿波发生电路,扫描时钟与地址发生时钟一致。由此完成一个示波器功能!-Through ADC0809 carried out on the analog signal sampling, and then a good 8-bit data conversion转存到rapid internal FPGA memory, at the same time increase the occurr
timer
- vhdl代码:电子时钟VHDL程序与仿真!初学fpga者可以参考参考!!比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple