搜索资源列表
13
- para13: fifo.vhd FIFO(双口RAM) fifo1.vhd FIFO(嵌入式EAB) fifo2.vhd FIFO(LPM)-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
sprp181_DM642_FPGA_HardDisk.pdf.tar
- DM642 接硬盘的方案,利用FPGA作FIFO缓冲,达到数据/图像/视频的实时高速写入。-DM642 access the hard disk of the program, the use of FPGA for FIFO buffer to data/images/video real-time high-speed write.
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
75448172geleicounter
- 这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
fifotop
- 基于FPGA编写的VHDL语言,FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
SOPC_Builder
- SOPC架构建立实例,针对altera公司的DE2开发板,其他开发系统也可以用-based FPGA , SOPC construct experiment
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
NIOS_JTAG_UART
- FPGA开发板上的JTAG——UART完成的工程设计,包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
fifi
- FIFO code written in VHDL
fpgafifo
- 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙,精简。 -vhdl fifo sound code
THS1206
- FPGA来实现数据采集,AD采用TI公司的THS1206,高速并行AD,内含16字FIFO,降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
fifo_test
- FIFO读写verilog程序,经本人验证,能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
yuyincaiji
- 语音采集与回放系统源代码:1.为了使读音数据存储的时间更长,速度更快,选用了256K*16Bit的SRAM;2.为了减少单片机的控制复杂度,使用了FPGA来控制SRAM的读写操作,节约了不少单片机的I/O资源;3.为了以后的高速数据存储,本设计中加入了fifo,其位宽及深度可在程序中自由设置,方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
Asynchronous_FIFO_v6_1
- 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
T2_USB_IN
- CY7C68013A提供的端口FIFO的读写操作,与普通FIFO读写操作方式一样。CY7C68013A为每个端口提供了“空”标志、“满”标志和“ 可编程级”标志。FPGA检测这些信号,用于控制读写的过程-CY7C68013A available port FIFO read and write operations, and general FIFO read and write operations the same way. CY7C68013A for each port provide
spartan6_fpga_blockram_user_guide
- Spartan6 FPGA中的块存储器使用指南,可以构建为FIFO,ROM,RAM,移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code