搜索资源列表
Grayscale-Conversion-IP
- Sobel Edge Detection IP for FPGA using LABVIEW
Image-Reduction-IP
- LABVIEW Program for Image REduction IP for FPGA
Bspii_masttera
- 一种基于CPLD/FPGA的的SPI控制的IP核的实现spi -Based on CPLD/FPGA IP core SPI control realize spi
vga_lcd
- VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
crc-ip-core-usage
- CRC 编译码IP核的使用方法，仿真图和matlab的结果对比对比，fpga编程时使用-CRC encoding and decoding IP core use simulation in Fig the Matlab results contrast contrast
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
FPGA-Communication-Framework-.tar
- 这是来自开源网站OpenCores的程序，版权归作者所有，仅供学习交流。一个上位机软件源程序，和一个FPGA硬件核的源程序（<600slices），上位机软件可以通过UDP/IP连通FPGA实现通信。-This is from the open source the website OpenCores the program belongs to the author, only learning exchanges. A host computer software source cod
Triple-Rate---DualLink-FPGA-IP-v-2.0-Jul-2008
- Parallel to 5 pair HDSDI encode/decode
FPGA-floating-Point-IP-cores
- Taking Advantage of Advances in FPGA floating-Point IP cores -Taking Advantage of Advances in FPGA floating-Point IP cores
ROM-MIF
- 利用MATLAB产生FPGA IP 核ROM，初始化文件，用来初始化ROM的MIF文件-Using MATLAB generates FPGA IP Core ROM, initialization files, MIF file is used to initialize the ROM
sqrt
- FPGA的一个IP内核，用来优化除法算法的源代码包。-An FPGA IP cores to optimize the division algorithm source code package.
div
- FPGA的IP核中除法算法的源代码，是Verilog语言的，易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
ZedBoard-step3-
- 一步 学ZedBoard & Zynq(三)：使用自带外设IP让ARM PS访问FPGA -Step by step learning ZedBoard & Zynq (three): Using its own peripheral access FPGA IP allows ARM PS
XILINX DDR2
- xilinx ddr2 ip核的verilog例子
fft256
- 利用FPGA ip核实现256点的FFT转换，用vhdL语言实现。-Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
top
- 调用FPGA中的IP核的RAM的顶层文件-Call the FPGA IP core RAM top-level file
Encryption-SATA-IP-Based-on-FPGA
- 本文首先分析了目前常用的硬盘数据加密方法，并在比较各种加密方案的基础上给出了基于FPGA的加解密SATA IP设计方案。本文介绍设计SATA IP相关的基础知识，包括SATA的体系结构。本sata IP已在Xilinx spartan-6系列上实现并产品化，具有低成本优势，且可以根据用户意愿更换加密算法和使用私有的加密算法。本文还论述了加密SATA IP的各种应用前景。-This paper firstly analyzes several common ways of Hard Disk da
HSDI-communcation-interface-IP
- 基于FPGA的HSDI接口的程序，调试可用。-FPGA-based programs HSDI interfaces, debug available.