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divider256
- 这是一个2至256分频器，可以将输进来的信号进行2至256次分频后输出，分频器的大小可选-This is a 2 to 256 frequency divider which can transfer the input clock signal into 1/2 to 1/256 clock
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
fenpin
- 这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
division
- 分频器,偶数分频 奇数分频 小数分频 不同方法实现不同种类分频 -Divider, even odd frequency divider fractional different ways to achieve different types of crossover
divider3
- 一个3分频器。可进一步改装成实际需要的分频器使用-a divider. Can be further converted into actual use of the Frequency Divider
divp5
- fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Airtight.tar
- 测试台的工控程序，主要控制继电器，LED灯，以及分频器-IPC test bed program, the main control relay, LED lights, and a frequency divider
LED-blinks
- 选择不同的时钟源，使 P3.7 连接的发光二极管闪烁。 （1）使用 XT2 时钟源，8MHz 频率，用定时器 A 分频，产生 1s 脉冲，使 P3.7 引脚的发光二极管闪烁。-Choose different clock sources, so P3.7 connected LED blinks. (1) using the clock source XT2, 8MHz frequency divider with the timer A, the pulse generating 1s,
divp5
- fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
vc
- 利用C语言设计出一个具有16分频、8分频、4分频和2分频功能的分频器-Using C language to design a divide with 16, 8, 4 and 2 frequency divider divider function
phase_add
- 分频器，实现任意频率的分频，只需修改频率控制字,已经经过多次验证-Divider to achieve any frequency divider, simply modify the frequency control word, has been repeatedly verified
clk1hz
- 分频电路 将电路分频为1赫兹 可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
div_freq
- 分频器，把一个特定的频率进行分频，从而得到自己想要的频率-Frequency divider, a specific frequency divider, you want to get the frequency
DivFrec
- Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
fp_prj
- 分频器，Verilog语音编写，quartus仿真过，可以利用使蜂鸣器发生-Frequency divider, Verilog speech writing, quartus simulation, can make use of the buzzer
frequency_divider
- Frequency Divider vhdl source code with test bench