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The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
f_adder
- 该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器-The project descr iption is a full adder can use this as a basis to build a number of full adder
zuheluojiquanjiaqi
- 组合逻辑全加器，在vhdl环境下的，我试过，可以运行。-The combinational logic full adder in VHDL environment, I tried, you can run.
fulladder
- Full Adder using VHDL
eda
- EDA实验报告 内含 交通灯 数字时钟 全加器 触发器 的 代码灯-The EDA lab report contains the code of the traffic lights digital clock full adder trigger light
89_full_adder
- 全加器。VHDL入门例程。3个源程序。好好练习啊-Full adder. Introduction to VHDL routines. 3 source. Ah good practice
eda1
- 原理图方式实现8位全加器，文件类型为gdf ，vhd 文件-8-bit full adder schematic way, the file type for the GDF vhd file
adder_tp
- 本代码包含四位全加器和四位全加器的测试平台。-The code contains four full adders and four full adder test platform.
eda_shiyanbaogao
- eda实验报告，包括全加器、四选一数据选择器、交通灯。-eda lab reports, including full-adder, four elected a data selector, traffic lights.
f_adder
- ise13.2环境下vhdl编写的全加器+仿真波形-ise13.2 vhdl prepared under the full adder+ simulation waveforms
qjq
- 通过ISE软件采用VHDL语言实现1位全加器的功能-Through the ISE software using VHDL language a full adder function
full_add4_ok_
- Learning FPGA students can see, this code USES VHDL language to write four full adder, not only can learn QUARTUS software, also can better enhance the digital circuit design.
FPGA
- 简单的三人表决、一位全加器、三八译码器的VHDL语言的实现-Three simple voting, a full adder, the three eight decoder ，use VHDL language
Half_Add_vhdl
- 全加器的硬件描述语言，给出了基础的涉及组成。-Full adder hardware descr iption language, gives the basic components involved.
4weiquanjiaqi
- 4位全加器由3个模块构成。首先，通过实例引用基本门级元件xor、and定义底层的半加器模块halfadder，接着实例引用两个半加器模块halfadder和一个基本或门元件or组合成为全加器模块fulladder，最后实例引用4个1位的全加器模块fulladder构成4位全加器的顶层模块-4 full adder by the three modules. First, the basic gate-level component instance references xor, and def
lqz6
- 这个程序可以实现用图形输入方式，实现一个4位二进制全加器。-This procedure can be achieved using graphical input, to achieve a 4-bit binary full adder.
or2a
- 使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮-A full adder design
S-Edit1
- Full Adder SEDIT Xilinx
S-Edit_SFA
- SDIT circuit for full adder
Lecture_11
- FULL ADDER IN VHDL POWERPOINT